Scalarize matrix and vector ports

Choice for how ports are generated when your Simulink model includes a port which is an array or matrix data type

Model Configuration Pane: SystemVerilog DPI / SystemVerilog Ports

Description

Choose how the SystemVerilog ports are generated when your Simulink^® model includes a port which is an array or matrix data type.

When selecting this box, each element in the array or matrix creates a scalar port in the generated SystemVerilog.

When clearing this box, the generated SystemVerilog ports preserve the array or matrix as defined in Simulink.

Settings

off (default) | on

Default value is off.

Programmatic Use

Parameter: DPIScalarizePorts

Type:

Values:off|on

Default: off

Version History

Introduced in R2013b