collectData

R2026b

Collect captured data from FPGA to host in nonblocking mode

Since R2022a

Syntax

capturedData = collectData(DC)

Description

Add-On Required: This feature requires the HDL Coder Support Package for Intel FPGA and SoC Devices add-on.

capturedData = collectData(DC) returns the captured data from an FPGA to the host machine in nonblocking capture mode. DC is a customized data capture object.

Note

The collectData function is not supported in blocking capture mode.

Examples

Collect Captured Data from FPGA

Before you use this example, you must have previously generated the customized data capture object, using the FPGA Data Capture Component Generator tool. You must also have integrated the generated IP code into your project and deployed it to the FPGA. The data capture object communicates with the FPGA over a JTAG cable. Make sure that the required cable is connected between the board and the host computer.

This example uses a generated object, datacapture, that defines two signals for data capture. Signal A is 16 bits and signal B is 8 bits. Both signals are also available for use in trigger conditions. The sample depth is 1024 samples.

Change the capture mode to nonblocking mode.

DC.CaptureMode = 'nonblocking';

Check the current status of the data capture object.

status = checkStatus(DC)

status = 

  struct with fields:

    CapturedWindows: 0
          RunStatus: 'Not started'
       TriggerStage: 0

Define a trigger condition to capture data when the signal B is equal to 10.

setTriggerCondition(DC,'B',true,10);

Call the data capture object to capture data on the specified trigger event.

[Capture_Window,Trigger_Position,dataOut] = DC();

Check the current status of the data capture object.

status = checkStatus(DC)

status = 

  struct with fields:

    CapturedWindows: 1
          RunStatus: 'Successfully captured data from FPGA'
       TriggerStage: 0

Collect captured data.

capturedData = collectData(DC)

Captured 1 windows of data from FPGA.

capturedData = 

  struct with fields:

      Capture_Window: [1024×1 uint32]
    Trigger_Position: [1024×1 logical]
                   A: [1024×1 uint16]
                   B: [1024×1 uint8]

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Output Arguments

capturedData — Captured data

structure

Captured data, returned as a structure containing a field for the Capture_Window signal, a field for the Trigger_Position signal, and a field for each signal obtained by FPGA data capture. The captured signal field is a vector of Sample depth values for each signal requested for data capture at generation time. The fields of the structure have these signal names.

• Capture_Window — This signal indicates the current capture window.

• Trigger_Position — This signal indicates the position of the trigger detection clock cycle within a capture buffer.

• All remaining fields — The signal names you specified at generation time.

Version History

Introduced in R2022a