Connection
How signals are connected when the module is instantiated
Model Configuration Pane: SystemVerilog DPI / SystemVerilog Ports
Description
Select how signals are connected when the module is instantiated.
Settings
Port list (default) | InterfaceDefault: Port list
- Port list
Generate a SystemVerilog module with a port list in the header, representing its interface.
- Interface
Generate a SystemVerilog interface, and a module using that interface.
Programmatic Use
Parameter:
DPIPortConnection |
| Type: |
Values:Port list|
Interface |
Default:Port list
|
Version History
Introduced in R2013b
