Verification with FPGA Hardware
These features provide connections between your FPGA board and your simulations in Simulink or MATLAB.
FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an Intel®, Microchip, or Xilinx® FPGA board.
FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.
AXI manager provides access to live on-board memory locations from MATLAB or Simulink. You must include the AXI manager IP in your FPGA design.