HDL Verifier™ lets you test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs. You can verify RTL against test benches running in MATLAB® or Simulink® using cosimulation with an HDL simulator. These same test benches can be used with FPGA and SoC development boards to verify HDL implementations in hardware.
HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx® and Intel® boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.
HDL Verifier generates verification models for use in RTL test benches, including Universal Verification Methodology (UVM) test benches. These models run natively in simulators that support the SystemVerilog Direct Programming Interface (DPI).
Set up and run a ModelSim® and MATLAB test bench session.
The steps for setting up an HDL Verifier session that uses Simulink to verify a simple VHDL model.
This example guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard.
Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation.
This example shows how to configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder or Embedded Coder™.
This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Choose a Test Bench for Generated HDL Code (HDL Coder)
Select a generated test bench.
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
HDL Verifier works with Simulink or MATLAB and HDL Coder™ and the supported FPGA development environment to prepare your automatically generated HDL code for implementation in an FPGA.
HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.
HDL Verifier works with Simulink Coder™ or MATLAB Coder to export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).