Supported VHDL Constructs When Generating Simulink Models from VHDL Code

R2026b

You can use importhdl function to generate a Simulink^® model from synthesizable VHDL^® code. To import VHDL code, you must use constructs that the importhdl function supports.

Supported VHDL Constructs

These tables list the supported VHDL constructs. If you use an unsupported construct, the function generates an error when parsing the input VHDL file. The importhdl can sometimes ignore the presence of certain constructs in the VHDL code. To learn more, see the Comments column of the table.

Entity and Architecture Declaration

VHDL Constructs	Supported?	Comments
Entity declaration	Yes	–
Architecture declaration	Yes	Does not support multiple architectures for single entities.
Port declaration	Yes	Does not support arrays of ports.
Signal declaration	Yes	–
Generic clause	Yes	–

Package and Library Declaration

VHDL Constructs	Supported?	Comments
Package declaration	Yes	Supports only type declarations and constants.
Type declaration	Yes	Supports only enumerations, integers, and arrays.
Package Body	No	–
Subtype declaration	No	–
Constant declaration	Yes	Does not support array of constants.
Variable declaration	Yes	–
Use clause	Yes	–
Library declaration	Yes	Supports only IEEE® and work library declarations. When you specify work library in VHDL code, make sure that VHDL file and work library are in the same folder and the library name must be work.

Component and Configuration Declaration

VHDL Constructs	Supported?	Comments
Configuration declaration	No	–
Configuration specification	Yes	Ignored
Component declaration	Yes	Ignored
Component instantiation	Yes	–

Data Types and Vectors

VHDL Constructs	Supported?	Comments
Integer declaration	Yes	–
Real declaration	No	–
String declaration	No	–
Bit_vector	Yes	–
Enumerated	Yes	Supports only 0 and 1 among character literals. Does not support arrays of enumerated types.
Std_logic	Yes	Does not support values other than 0 and 1, such as U, X, Z, W, L, H.
Vector declaration	Yes	–

Identifiers and Comments

VHDL Constructs	Supported?	Comments
Numbers (based, normal)	Yes	Does not support real numbers that have decimal points.
Identifiers	Yes	Does not support extended identifiers.
Standard package functions	Yes	Supports only resize, to_std_logic_vector, to_integer, to_signed, and to_unsigned.
Attribute specification	No	–
Attribute declaration	No	–
Records	No	–
Comments(Block and Single line)	Yes	–

Assignments

VHDL Constructs	Supported?	Comments
Assignment statements (signal, variable)	Yes	–
Selected signal assignment	No	–
Aggregate assignment	Yes	Aggregate assignments on signal by using generic parameters are not supported.

Operators

VHDL Constructs	Supported?	Comments
Arithmetic operators (+,-,*, mod)	Yes	Does not support the remainder (rem) operator.
Relational operators (<, >, <<. >>)	Yes	–
Unary operators (+,-)	Yes	–
Logical operators (and, or, xor, nand, and nor)	Yes	–
Absolute and exponential operators (abs, **)	Yes	–
Shift operators (sll, srl, sla, sra, rol, and ror)	Yes	–

Conditional and Looping Statements

VHDL Constructs	Supported?	Comments
If-else statement	Yes	–
Case statement	Yes	–
Condition operators (??)	No	–
Assertion statements	No	–
For loop	Yes	Parameter specifications that use a discrete subtype, such as enumerations, are not supported.
Loop statements	No	–
Generate statement	No	Supports only the for generate statement.

Process Statements and Procedure Definitions

VHDL Constructs	Supported?	Comments
Process statement	Yes	–
Functions	No	–
Blocks	No	–
Procedure definitions	No	–
Function calls	No	–

Event Control Statements

VHDL Constructs	Supported?	Comments
Waveform condition	Yes	Time expressions are not supported.
Wait statement	Yes	Only supports wait statements that only use the until clause.
Exit statement	No	–
Null statement	No	–
Return statement	No	–

Limitations and Considerations

VHDL import does not support:

• Importing of VHDL files from a read-only folder.

• Generation of the preprocessing files in a read-only file system that parses the HDL code you input to the importhdl function.

• Element associations with range choice and mixed choices.

• Multiple architectures associated with single entity.

• More than one clock signal.

• Modules that are multirate.

• Recursive entity instantiation.

• Multiport Switch inference with more than 1024 inputs. If you specify more than 1024 inputs in function in the VHDL code that the importhdl function imports as a Multiport Switch block, the VHDL import generates an error. The Simulink modeling environment does not support more than 1024 inputs for the block.

• ROM detection from the VHDL code.

• Concatenation operation to evaluate reset value.