Generate HDL and HLS Code from a Packetized Transmit Logic Algorithm
R2026bThis example shows how to generate HDL and HLS code from a MATLAB® function that implements packetized transmit logic.
Packetized transmit logic is common in applications that model digital transmission paths. Hardware transmission systems structure outgoing data by inserting padded data, training sequences, payload information, and error-detection fields into a serialized stream. Control logic determines when each packet region is active and outputs one symbol per cycle.
Examine the MATLAB Design and Test Bench
Set up the MATLAB function and test bench for this example. In the MATLAB Command Window, enter:
mlhdlc_demo_setup("mlhdlc_comms_data_packet");MATLAB function
Test bench
Training and supporting data files
<model>_runme.mscript, which includes the commands to generate HDL code<model>_runme_hls.mscript, which includes the commands to generate HLS code
The MATLAB function, mlhdlc_comms_data_packet, implements a
packetizer for binary communication transmission. It outputs one symbol per call and
constructs packets in a fixed sequence: padding, training, payload, and a 16-bit CRC (cyclic
redundancy check). You can configure the pad length, training length, and payload length by
specifying them as input arguments. The function requests payload bytes from an external
first in first out (FIFO) buffer one at a time and outputs the variable
reByte. You can apply differential encoding to the payload and CRC
regions.
To view the function, enter:
open mlhdlc_comms_data_packet.m;The test bench file, mlhdlc_comms_data_packet_tb, verifies the
behavior of the MATLAB function. To view the test bench,
enter:
open mlhdlc_comms_data_packet_tb;The example also includes mlhdlc_comms_data_packet_training_data.txt,
which contains the numeric values for the training sequence. The test bench loads this file
to generate the training data for packet transmission.
Simulate the Design
To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:
mlhdlc_comms_data_packet_tb;
Generate HDL Code
The mlhdlc_comms_data_packet_runme script specifies the target files,
enables the settings required for this example, and generates HDL code.
The script specifies the MATLAB function and test bench, then creates a fixed-point
configuration object and an HDL configuration object by using the
coder.config function. It associates the test bench with both
configuration
objects.
designName = "mlhdlc_comms_data_packet"; designTB = "mlhdlc_comms_data_packet_tb"; fixptCfg = coder.config("fixpt"); fixptCfg.TestBenchName = designTB; cfg = coder.config("hdl"); cfg.TestBenchName = designTB;
The script then generates code:
codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, "-launchreport");
Run the Script
First, modify the mlhdlc_comms_data_packet_runme script. Synthesis
is disabled by default. Change the value for the
SynthesizeGeneratedCode
property:
cfg.SynthesizeGeneratedCode = true;
Update the settings for your synthesis tool:
cfg.SynthesisTool = "Xilinx Vivado"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I";
Then, generate code by running the script:
mlhdlc_comms_data_packet_runme
After code generation completes, the report opens. Examine the generated HDL code in the report.
Generate HLS Code
The mlhdlc_comms_data_packet_runme_hls script specifies the target
files, enables the settings required for this example, and generates HLS code.
The script specifies the MATLAB function and test bench, then creates a fixed-point
configuration object and an HLS configuration object by using the
coder.config function. It associates the test bench with both
configuration
objects.
designName = "mlhdlc_comms_data_packet"; designTB = "mlhdlc_comms_data_packet_tb"; fixptCfg = coder.config("fixpt"); fixptCfg.TestBenchName = designTB;
The script creates an HLS configuration object by using the
coder.config function, associates the test bench, and enables
simulation.
cfg = coder.config("hls");
cfg.TestBenchName = designTB;
cfg.SimulateGeneratedCode = true;The script then generates code:
codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, "-launchreport");
Run the Script
First, modify the mlhdlc_comms_data_packet_runme_hls script.
The script disables synthesis by default. Change the value for the
SynthesizeGeneratedCode
property:
cfg.SynthesizeGeneratedCode = true;
Depending on your synthesis tool, set one of these flags to
true:
isCodingForStratusHLS = false; isCodingForVitisHLS = true;
Depending on your synthesis tool, update these synthesis tool settings:
if isCodingForStratusHLS cfg.SynthesisTool = "Cadence Stratus HLS"; elseif isCodingForVitisHLS cfg.SynthesisTool = "Xilinx Vitis HLS"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I"; end
Then, generate code by running the script:
mlhdlc_comms_data_packet_runme_hls
After code generation completes, the report opens. Examine the generated HLS code in the report.