Configure Software Interface to FPGA

Configure a software interface model to connect your designed IP core and to deploy to the embedded processor of your target hardware

Create a software interface model that contains the algorithm to run on the embedded processor on your target platform. The input is your tested and verified IP core model. The output is the software interface model containing the communication between the FPGA and processor and the algorithm that deploys to the embedded processor on-board your SoC device or Simulink^® Real-Time™ target machine. For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Configure Hardware Software Interface Workflow

Topics

Generate Software Interface Model to Probe and Rapidly Prototype HDL IP Core
Generate software interface model to communicate with the HDL IP core and perform rapid prototyping.
Generate Device Tree for IP Core
Generate device tree files that include the HDL Coder™ generated IP core.

Featured Examples

Debug a Zynq Design Using HDL Coder and Embedded Coder

Debug a Zynq® design using HDL Coder™ and Embedded Coder® features.

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Model and Debug Test Point Signals with HDL Coder

An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.

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Running an Audio Filter on Live Audio Input Using a Zynq Board

Model an audio system and implement it on a Zynq® board using an audio reference design.

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