Euler to NED Transformation HDL Optimized
Computes Euler to NorthEastDown transformation using pipelined or burst architecture and generates optimized HDL code
Since R2022b
Libraries:
FixedPoint Designer HDL Support /
Coordinate Transformations
Description
The Euler to NED Transformation HDL Optimized block provides two architectures that implement Euler to NorthEastDown (NED) transformation using a CORDIC rotation kernel for FPGA and ASIC applications.
You can select an architecture that optimizes for either throughput or area.
Pipelined
— Use this architecture for highthroughput applications.Burst
— Use this architecture for a minimum resource implementation.
The Euler to NED Transformation HDL Optimized block provides hardwarefriendly control signals.
Ports
Input
U In — Input array
3by1 vector
Input array, specified as a 3by1 vector.
Fixedpoint inputs must use binarypoint scaling.
Example:
UIn = [0;0;1]
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Complex Number Support: Yes
Angle In — Angles to rotate by
3by1 vector
Angles to rotate by, specified as a 3by1 realvalued vector containing the angles phi, theta, and psi in radians.
Example:
AngleIn = [phi;theta;psi]
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Valid In — Whether input is valid
Boolean
scalar
Whether input is valid, specified as a Boolean scalar. This control signal
indicates when the data from the U In and Angle
In input ports are valid. When this value is 1
(true
), the block captures the values at the input ports
U In and Angle In. When this value is
0
(false
), the block ignores the input
samples.
Data Types: Boolean
Restart — Whether to clear internal states
Boolean
scalar
Whether to clear internal states, specified as a Boolean scalar. When this value
is 1 (true
), the block stops the current calculation and clears all
internal states. When this value is 0 (false
) and the
Valid In value is 1 (true
), the block begins
a new subframe.
Data Types: Boolean
Output
U Out — Rotated array
3by1 vector
Rotated array, returned as a 3by1 vector.
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Valid Out — Whether output data is valid
boolean scalar
Whether the output data is valid, returned as a Boolean scalar. When the value of
this control signal is 1
(true
), the block has
successfully computed the output U Out. When this value is
0
(false
), the output data is not
valid.
Data Types: Boolean
Ready — Whether block is ready for input
Boolean
scalar
Whether the block is ready for input, returned as a Boolean scalar. This control
signal indicates when the block is ready for new input data. When this value is 1
(true
) and Valid In value is 1
(true
), the block accepts input data in the next time step. When
this value is 0 (false
), the block ignores input data in the next
time step.
Data Types: Boolean
Parameters
Architecture — Architecture type
Pipelined
(default)  Burst
This parameter specifies the type of architecture.
Pipelined
— Select this value to specify lowlatency architecture.Burst
— Select this value to specify minimum resource architecture.
Programmatic Use
Block Parameter:
Architecture 
Type: character vector 
Values:
'Pipelined'  'Burst' 
Default:
'Pipelined' 
Algorithms
EulerNED Transformation
The Euler to NorthEastDown (NED) transformation is carried out by the successive application of these three rotation matrices.
$$\begin{array}{l}{R}_{\varphi}=\left[\begin{array}{ccc}1& 0& 0\\ 0& \mathrm{cos}(\varphi )& \mathrm{sin}(\varphi )\\ 0& \mathrm{sin}(\varphi )& \mathrm{cos}(\varphi )\end{array}\right]\\ {R}_{\theta}=\left[\begin{array}{ccc}\mathrm{cos}(\theta )& 0& \mathrm{sin}(\theta )\\ 0& 1& 0\\ \mathrm{sin}(\theta )& 0& \mathrm{cos}(\theta )\end{array}\right]\\ {R}_{\psi}=\left[\begin{array}{ccc}\mathrm{cos}(\psi )& \mathrm{sin}(\psi )& 0\\ \mathrm{sin}(\psi )& \mathrm{cos}(\psi )& 0\\ 0& 0& 1\end{array}\right]\end{array}$$
Multiplying these matrices together gives the total transformation.
$$\begin{array}{c}A={R}_{\psi}{R}_{\theta}{R}_{\varphi}\\ =\left[\begin{array}{ccc}\mathrm{cos}(\psi )\mathrm{cos}(\theta )& \mathrm{cos}(\psi )\mathrm{sin}(\varphi )\mathrm{sin}(\theta )\mathrm{cos}(\varphi )\mathrm{sin}(\psi )& \mathrm{sin}(\varphi )\mathrm{sin}(\psi )+\mathrm{cos}(\varphi )\mathrm{cos}(\psi )\mathrm{sin}(\theta )\\ \mathrm{cos}(\theta )\mathrm{sin}(\psi )& \mathrm{cos}(\varphi )\mathrm{cos}(\psi )+\mathrm{sin}(\varphi )\mathrm{sin}(\psi )\mathrm{sin}(\theta )& \mathrm{cos}(\varphi )\mathrm{sin}(\psi )\mathrm{sin}(\theta )\mathrm{cos}(\psi )\mathrm{sin}(\varphi )\\ \mathrm{sin}(\theta )& \mathrm{cos}(\theta )\mathrm{sin}(\varphi )& \mathrm{cos}(\varphi )\mathrm{cos}(\theta )\end{array}\right]\end{array}$$
You can transform between two frames related by the angles ϕ, θ
, and ψ by multiplying a vector in an initial frame by the matrix above.
CORDIC Algorithm
CORDIC is an acronym for COordinate Rotation Digital Computer. The Givens rotationbased CORDIC algorithm is one of the most hardwareefficient algorithms available because it requires only iterative shiftadd operations. It is an iterative algorithm that approximates the solution by converging toward the ideal point. Using CORDIC, you can calculate various functions such as sine and cosine.
To use CORDIC to solve the EulerNED transformation, CORDIC Givens rotations are applied sequentially in the appropriate subspaces of the initial space. First, rotate by ϕ in the yzplane, then rotate by θ in the xzplane, then rotate by ψ in the xyplane.
Performance
This resource and performance data is the synthesis result from the generated HDL targeted to a Virtex^{®}7.
Algorithm  Flip Flops  LUT  LUTRAM  DSPs 

Pipelined CORDIC (sfix14En10)  3141  86  3973  0 
Resource Shared CORDIC (sfix14En10)  337  659  0  0 
Algorithm  Clock Frequency (MHz)  Latency (Cycles)  Latency (ns) 

Pipelined CORDIC (sfix14En10)  347  63  181 
Resource Shared CORDIC (sfix14En10)  347  57  164 
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Supports fixedpoint data types only. Fixedpoint data types must use binarypoint scaling.
Generated C/C++ code will have timing of the HDL block.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
General  

ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Supports fixedpoint data types only. Fixedpoint data types must use binarypoint scaling.
FixedPoint Conversion
Design and simulate fixedpoint systems using FixedPoint Designer™.
Version History
Introduced in R2022b
See Also
MATLAB 명령
다음 MATLAB 명령에 해당하는 링크를 클릭했습니다.
명령을 실행하려면 MATLAB 명령 창에 입력하십시오. 웹 브라우저는 MATLAB 명령을 지원하지 않습니다.
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