HDL Code Generation
To implement a DSP design on FPGAs or ASICs, you can use either HDL Coder™ or Filter Design HDL Coder™. Both products generate synthesizable and portable VHDL® and Verilog® code, and also generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code.
HDL Coder — Generate code from Simulink or MATLAB designs. This support includes filters, math and signal operations, and other algorithms optimized for resource use and performance, such as the FFT HDL Optimized, IFFT HDL Optimized, and NCO HDL Optimized blocks. For a basic example of how to generate HDL code using HDL Coder, see Programmable FIR Filter for FPGA.
Filter Design HDL Coder — Generate code from MATLAB filter designs. You can access code and test bench generation features using the Generate HDL user interface, or by using command-line options. These features are also integrated with the Filter Designer app. For an example of how to generate HDL code using Filter Design HDL Coder, see HDL Butterworth Filter (Filter Design HDL Coder).
To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.
Simulink Visualization Tool
|Logic Analyzer||Visualize, measure, and analyze transitions and states over time|
|Generate HDL code for quantized DSP filter (requires Filter Design HDL Coder)|
Filter for blocks that support HDL code generation in the Simulink library browser and in documentation.
Generate HDL Code for Filter System Objects (Filter Design HDL Coder)
Learn about the specifics of HDL code generation from filter System objects.
Select HDL code generation parameters to control speed vs. area tradeoffs in filter architectures.
Select resource sharing and pipeline optimization options.
Choose a block that supports frame-based input for HDL code generation.
Visualize multiple signals of a programmable FIR filter by using a logic analyzer.