C28x-Watchdog

When enabled, if the software fails to reset the watchdog counter within a specified interval, the watchdog resets the processor or generates an interrupt. This feature enables the processor to recover from faults.

For more information, see the Data Manual or System Control and Interrupts Reference Guide for your processor on the Texas Instruments™ website.

Enable watchdog

Enable the watchdog timer module.

This parameter corresponds to bit 6 (WDDIS) of the watchdog control register (WDCR) and bit 0 (WDOVERRIDE) of the system control and status register (SCSR).

Counter clock

Set the watchdog timer period relative to OSCCLK/512.

This parameter corresponds to bits 2–0 (WDPS) of the watchdog control register (WDCR).

Note

Depending on the processor type, the default value of the watchdog clock (WDCLK) can be based on the internal oscillator (INTOSC1) or external oscillator (OSCCLK).

Timer period ((1/Counter clock)*256) in seconds

Display the timer period in seconds. This value automatically gets updated when you change the Counter clock parameter.

Time out event

Configure the watchdog to reset the processor or generate an interrupt when the software fails to reset the watchdog counter. The available options are:

  • Chip reset—Generates a signal (WDRST) that resets the processor and disables the watchdog interrupt signal (WDINT).

  • Raise WD Interrupt—Generates a watchdog interrupt signal (WDINT) and disables the reset processor signal (WDRST). The WDINT signal can be used to wake the device from an idle or standby low-power mode.

This parameter corresponds to bit 1 (WDENINT) of the system control and status register (SCSR).

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