Detect and Capture Wideband Radar Signal Using Xilinx RFSoC Device

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This example shows how to build, simulate, and deploy a wideband radar signal detection and capture system in Simulink®. You use an SoC Blockset™ implementation and use it to target the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit. Using this example, you can detect radar signals over a 2 GHz bandwidth and capture the detected signals for further analysis. You partition the wideband radar signal detection and capturing functionality across the FPGA and the processor on the RFSoC device. The FPGA handles the wideband signal processing and the processor handles the system control, configuration, and status update. You also implement a radar emulator to generate pulsed radar signals and use these signals to evaluate the wideband detection and capturing capability of the system.

Supported Hardware Platforms

Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit with an XM500 balun card.

Design Task

Radar signal detection is an important part of electronic warfare systems. Radar operators can detect radar emitters in the vicinity of key value installations and take appropriate countermeasures. In this example, you design a wideband radar signal detector system to detect and capture radar signals and identify the characteristics of the radar. The receiver monitors the entire spectrum of interest and identifies the narrowband channels containing valid signals. The receiver then captures the signals and transfers them to the host MATLAB® over FPGA I/O. You can then visualize and analyze the signals. The design also integrates a radar signal generator to transmit test signals for validating the signal detection functionality.

In this example, the design task is to model the complete wideband radar system in an SoC Blockset model and implement the system on an RFSoC device. The system consists of a radar signal test transmitter, a wideband receiver, and a detector. The transmitter generates a train of linear frequency-modulated (LFM) pulses and transmits them through one of the DAC channels on the RFSoC device. You can configure the transmitter parameters during the design phase or after deployment. The receiver receives the radar signal and applies an energy detection algorithm to identify and extract the signal of interest. In this example, you pass the wideband input signal through a channelizer to separate the individual channels of interest. You then identify the active channels using thresholding.

System Specifications

The system has these high-level specifications:

Receiver instantaneous bandwidth of 2 GHz
64 receiver channels
Receiver channel bandwidth of 30 MHz

This figure shows the implementation block diagram of the system.

Design Radar Signal Detector

Create the soc_radar_signal_detector_top SoC model as the top model and set the hardware board to the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit. This model includes the soc_radar_signal_detector_fpga FPGA model and the soc_radar_signal_detector_proc processor model as model references. The top model also includes an AXI4-Stream to Software block, which shares the external memory between the FPGA and the processor.

open_system('soc_radar_signal_detector_top')

close_system('soc_radar_signal_detector_top')

RF Data Converter Configuration

RFSoC devices have an RF Data Converter hardware IP connected to the programmable logic, which you configure according to your needs. Use the RF Data Converter (RFDC) block to configure the ADC and DAC settings of the Xilinx RF Data Converter IP and emulate the programmable logic interface to the converters.

To meet the system requirements of 2 GHz of bandwidth, configure the RF Data Converter block by following these steps.

1. Choose the decimation factor and ADC sample rate based on the instantaneous bandwidth specification.

To achieve an instantaneous bandwidth of 2 GHz, set Sample rate (MSPS) to 4096. This value is the lowest sampling rate satisfying the Nyquist criterion that you can derive from the RF PLL reference on the ZCU111 board.

To achieve an instantaneous bandwidth of 2048 MHz, set the Decimation mode to 1 and Interpolation mode to 1.

2. Set Samples per clock cycle to 16 so that the FPGA clock rate is 256 MHz. The FPGA clock rate is the sampling rate divided by the product of the decimation factor and the number of samples per clock cycle, which in this case is equal to (4096/16) MHz, or 256 MHz.

3. To select specific ADCs and DACs, set RF Interface to Customize. To user the real interface, set the Digital interface to Real.

4. Select ADC 0 in ADC Tile 0 and DAC 2 in DAC Tile 1.

The ZCU111 evaluation board comes with an XM500 eight-channel SMA breakout card. This card has two ADC and two DAC single-ended channels (ADC224_T0_CH0, ADC224_T0_CH1, DAC229_T1_CH2, and DAC229_T1_CH3) for supporting a frequency range of 10 MHz to 1 GHz.

Hardware Logic Design

The soc_radar_signal_detector_fpga FPGA model contains two subsystems: Pulse Generator and Wideband Detector.

open_system('soc_radar_signal_detector_fpga')

close_system('soc_radar_signal_detector_fpga')

The Pulse Generator subsystem consists of the Pulse Generator Control and NCO LFM Generator subsystems. Use the Pulse Generator Control subsystem to define parameters that determine the timing of the signal generator, number of pulses, pulse repetition interval (PRI), and pulse width. You can configure these parameters at run time over an AXI4-Lite connection. The NCO LFM Generator subsystem then generates the linear FM waveform using a vector-based NCO. Use this subsystem to set parameters that determine the frequency characteristics of the waveform, such as the starting frequency and frequency step size.

The Wideband Detector subsystem implements the core receiver signal processing. The Channelizer block filters the wideband input signal from the ADC into the 64 narrowband channels. The Compute Power block then computes the power in each of the channels. The Detector block computes the moving average of the channel power levels and identifies that a signal is present when the current power is significantly greater than the moving average. When the block detects a signal, it selects the channel containing the highest power and provides the channel index to the subsequent processing blocks. The Output Capture block captures the channelized I/Q data from the channel containing the strongest signal. The To DMA Interface block sends the captured data packet to the processor.

Processor Logic Design

The soc_radar_signal_detector_proc processor model contains two subsystems: Pulse Generator Update and DMA Read Sim.

The Pulse Generator subsystem runs for every 0.2 seconds according to the PulseGenConfigTask defined in Task Manager block.

PulseGenConfigTask

Type of task - Timer.
Task period - 0.2 s.
Function - Control the timing execution of the software.

The DMA Read Sim subsystem reads the DMA packet from the FPGA and displays the detected signal.

open_system('soc_radar_signal_detector_proc')

close_system('soc_radar_signal_detector_proc')

Simulate Radar Detection System

Run the model to visualize the detected signal and validate it against the transmitted radar waveform characteristics.

Implement and Run Model on Hardware

Configure Hardware

Connect the SMA connectors on the XM500 Balun card to complete the loopback between the DAC and ADC channels, according to these connections and the same shown in the figure.

DAC229_T1_CH2(J5) to ADC224_T0_CH0(J4).

To implement the model on a supported SoC board, use the SoC Builder tool. Set the Hardware Board to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit on the System on Chip tab of the Simulink toolstrip.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

On the Setup screen, select Build model. Click Next.
On the Select Build Action screen, select Build and load for external mode. Click Next.
On the Select Project Folder screen, specify the project folder. Click Next.
On the Review Hardware Mapping screen, click Next.
On the Review Memory Map screen, to view the memory map, click View/Edit. Click Next.
On the Validate Model screen, to check the compatibility of the model for implementation, click Validate. Click Next.
On the Build Model screen, to build the model, click Build. An external shell opens when FPGA synthesis begins. Click Next.
On the Connect Hardware screen, to test the connectivity of the host computer with the SoC board, click Test Connection. To go to the Run Application screen, click Next.

The FPGA synthesis often takes more than 30 minutes to complete. To save time, you can use a pre-generated bitstream by following these steps.

Close the external shell to terminate the FPGA synthesis.
Copy the pre-generated bitstream to your project folder by entering this command at the MATLAB command prompt.

copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot,
'toolbox','soc','supportpackages','xilinxsoc','xilinxsocexamples','bitstreams',
'soc_radar_signal_detector_top-XilinxZynqUltraScale_RFSoCZCU111EvaluationKit.bit'),'./soc_prj');

Validate FPGA Design

Click Load and Run to load the pre-generated bitstream. You can use the automatically generated FPGA I/O script during the build process to quickly verify the FPGA algorithm. To validate the FPGA algorithm, load the bitstream and follow these steps.

1. Open the soc_radar_signal_detector_host_run_capture_io script.

soc_radar_signal_detector_host_run_capture_io

2. Set the ZCU111 board IP address in the IPAddress field. 3. Run the script by clicking the Run button.

The script generates a plot containing the captured pulse in the time and frequency domains. The default value of the PRI is 50 microseconds. The pulse has a duration of 10 microseconds, a start frequency of 1305 MHz, and an end frequency of 1320 MHz. The estimated PRI, pulse duration, and pulse start and end frequencies must match the default settings.

Verify System in External Mode

You can now run the model in external mode or deploy the complete system, consisting of the processor and FPGA algorithms, onto hardware and verify the functionality.

After you load the bit file, close the generated software model and open the soc_radar_signal_detector_pulsegen_interface software model.

open_system('soc_radar_signal_detector_pulsegen_interface')

close_system('soc_radar_signal_detector_pulsegen_interface')

Run the model in external mode by clicking Monitor & Tune. After the model runs on hardware, run the soc_radar_signal_detector_host_run_capture_io script, ensuring that the hardware board IP address is correct. The detection information includes the detected radar PRI, as well as time and spectrum plots of the captured signal.

You can try updating the PRI, pulse duration, and pulse start and end frequencies with different values from the software model. You can then check whether the wideband detector detects the resultant characteristics and whether the hardware captures them adequately.

Conclusion and Further Exploration

This example shows how to integrate a wideband radar signal detection system on a Xilinx ZCU111 evaluation board using SoC Blockset software. The example shows how to verify the design in a simulation and on hardware. The implementation detects a signal from a wideband channel, detects the characteristics, and captures the signal for further analysis.