Modeling
R2026bModel and simulate applications for AMD® SoC devices by preparing your design for hardware execution and incorporating Simulink® blocks that support hardware communication and operating system interactions.
Blocks
 | AXI4-Interface Read | Read data from IP core on AMD SoC Device |
 | AXI4-Interface Write | Write data to IP core on AMD SoC Device |
 | Linux Task | Spawn task function as separate Linux thread |
 | UDP Receive | Receive UDP data |
 | UDP Send | Send UDP message |
 | VxWorks Task | Spawn task function as separate VxWorks thread |
 | AXI4-Stream IIO Write | Write AXI4-Stream Data using IIO |
 | AXI4-Stream IIO Read | Read AXI4-Stream Data using IIO |
Model Settings
Functions
zynqlib | Open the Simulink Library Browser to the SoC Blockset Support Package for AMD FPGA and SoC Devices block library |
Topics
- Supported Features for Embedded Targets
List of supported features for AMD SoC devices.
- Choose a Method to Interact with IP Cores on Target Hardware (HDL Coder)
Choose a software interface method to interact with IP cores running on target hardware.
- Processor and FPGA Synchronization (HDL Coder)
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you generate a custom IP core to use in an embedded system integration project.
Featured Examples
Get Started With Code Generation Using SoC Blockset Support Package for AMD SoC Devices
Generate code from a Simulink model and run the executable on an AMD Zynq® board.
Communicate with AMD Zynq Boards Using UDP Protocol
Send data from a Simulink® model running on an ARM® Cortex®-A processor in an AMD Zynq® platform to another model running on the host computer by using the UDP ethernet protocol.
Basic Control Algorithm Partitioned into FPGA and ARM
Model a field-oriented controller (FOC) for a permanent magnet synchronous machine (PMSM) on the Zynq UltraScale+™ MPSoC target.
