Assertion
Check whether signal is zero
Libraries:
Simulink /
Model Verification
HDL Coder /
Model Verification
Description
The Assertion block checks whether any of the elements of the input
signal are 0
. If all of the elements are nonzero, the assertion is
true (1)
and the block does nothing. If not, the block halts the
simulation and returns an error message by default.
Ports
Input
Parameters
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
Version History
Introduced before R2006a