코드 생성
코드에서 C/C++ 실행 코드와 MEX 함수를 생성할 수 있습니다. 코드 생성을 지원하는 함수와 System object의 목록은 함수 목록(C/C++ 코드 생성) 항목을 참조하십시오.
HDL 코드를 생성하고 이 코드를 ASIC(Application-Specific Integrated Circuit, 주문형 반도체) 또는 FPGA(Field-Programmable Gate Array)에 배포하여 Simulink® 모델이나 서브시스템을 하드웨어에 구현할 수 있습니다. 아래 예제에서는 Simulink 모델에서 HDL 코드를 생성하는 방법을 보여줍니다. Simulink 모델에서 HDL 코드를 생성하는 방법에 대한 자세한 내용은 HDL Code Generation from Simulink (HDL Coder) 항목을 참조하십시오.
도움말 항목
- Code Generation
Using code generation with the Phased Array System Toolbox™.
- FPGA-Based Beamforming in Simulink: Algorithm Design
This example shows the first half of a workflow to develop a beamformer in Simulink® suitable for implementation on hardware, such as a field programmable gate array (FPGA).
- FPGA-Based Beamforming in Simulink: Code Generation
This workflow generates HDL code for a beamforming algorithm and verifies that the generated code is functionally correct.
- Generate MEX Function to Estimate Directions of Arrival
Estimate signal directions of arrival.
- Generate MEX Function Containing Persistent System Objects
Make System Objects persistent.
추천 예제
Audio Beamforming on a Multicore Processor
Implement a real-time audio beamforming application on a multicore processor.
Beamscan Direction of Arrival Estimation Using FPGA
Estimate direction of arrival (DOA) by using a beamscan technique suitable for implementation on hardware.
Rectangular Array MVDR Beamformer
Implement a minimum-variance distortionless-response (MVDR) beamformer for a 4x4 rectangular antenna array on FPGA.
FPGA-Based Uniform Linear Array MVDR Beamformer
Implement a fixed-point HDL-optimized minimum-variance distortionless-response beamformer.
FPGA-Based Monopulse Technique: Algorithm Design
Develop a monopulse technique to perform digital down-conversion (Part 1).
FPGA-Based Monopulse Technique: Code Generation
Develop a monopulse technique to perform digital down-conversion (Part 2).
FPGA-Based Cell-Averaging Constant False Alarm Rate (CA-CFAR) Detector
Design a FPGA implementation-ready CA-CFAR detector.
