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Verify Viterbi Decoder Using MATLAB System Object and HDL Simulator

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This example shows you how to use MATLAB® System objects and an HDL simulator to cosimulate a Viterbi decoder implemented in VHDL.

The HDL Verifier™ product lets you verify the design implemented in Verilog or VHDL using MATLAB System objects. The product allows you to cosimulate the HDL code with MATLAB and verify the model against the HDL implementation. This example uses MATLAB System objects and following HDL simulators to cosimulate a Viterbi decoder.

  • Vivado® Simulator from AMD®

  • ModelSim™ or Questa™ from Siemens EDA

  • Xcelium® from Cadence®

Set Simulation Parameters and Instantiate Communication System Objects

If you are using Xcelium, set simulator variable to Xcelium.

Simulator = 'Xcelium';

If you are using ModelSim/QuestaSim, set simulator variable to ModelSim.

Simulator = 'ModelSim';

If you are using Vivado simulator The HDL cosimulation System object™ for Vivado simulator can be created by using the Cosimulation Wizard tool only. For more information on the Cosimulation Wizard tool, see Cosimulation Wizard.

The following code sets up the simulation parameters and instantiates the System objects that represent the channel encoder, BPSK modulator, AWGN channel, BPSK demodulator, and error rate calculator. Those objects comprise the system around the Viterbi decoder and can be thought of as the test bed for the Viterbi HDL implementation.

EsNo = 0;	% Energy per symbol to noise power spectrum density ratio in dB

FrameSize = 1024;  % Number of bits in each frame

Convolution Encoder

hConEnc = comm.ConvolutionalEncoder;

BPSK Modulator

hMod    = comm.BPSKModulator;

AWGN channel

hChan   = comm.AWGNChannel('NoiseMethod', ...
                         'Signal to noise ratio (Es/No)', ...
                         'SamplesPerSymbol',1, ...
                         'EsNo',EsNo);

BPSK demodulator

hDemod  = comm.BPSKDemodulator('DecisionMethod','Log-likelihood ratio', ...
                            'Variance',0.5*10^(-EsNo/10));

Error Rate Calculator

hError  = comm.ErrorRate('ComputationDelay',100,'ReceiveDelay',58);

Instantiate Cosimulation System Object and Launch HDL Simulator

For ModelSim or Xcelium

1. The HDL cosimulation System object for ModelSim or Xcelium can be created by using either the Cosimulation Wizard tool or hdlcosim function. This example uses the hdlcosim function to generate the HDL cosimulation System Object. The System object represents the HDL implementation of the Viterbi decoder in this simulation system. The object's interface is common for all simulators. As a convenience to avoid writing some HDL testbench code, we generate waveforms for the clocks and resets using simulator-specific Tcl code.

hDec = hdlcosim('InputSignals', {'/viterbi_block/In1','/viterbi_block/In2'}, ...
              'OutputSignals', {'/viterbi_block/Out1'}, ...
              'OutputSigned', false, ...
              'OutputFractionLengths', 0, ...
              'TCLPostSimulationCommand', 'echo "done";', ...
              'PreRunTime', {10,'ns'}, ...
              'Connection', {'Shared'}, ...
              'SampleTime', {10,'ns'});

switch Simulator
  case 'ModelSim'
      hDec.TCLPreSimulationCommand = ...
          'force /viterbi_block/clk_enable 1 0; force /viterbi_block/clk 0 0 ns, 1 5 ns -repeat 10 ns; force /viterbi_block/reset 1 0 ns, 0 8 ns; ';
  case 'Xcelium'
      hDec.TCLPreSimulationCommand = ...
          'force :clk B"0" -after 0ns B"1" -after 5ns -repeat 10ns; force reset B"1" -after 0ns B"0" -after 8ns; force :clk_enable B"1" -after 0ns';
end

2. The vsim and nclaunch command launches HDL simulator. The launched HDL simulator session compiles the HDL design and loads the HDL simulation. You are ready to perform cosimulation when the HDL simulation is fully loaded in simulator.

disp('Launching HDL simulator...');
switch Simulator
  case 'ModelSim'
      vsim('tclstart',viterbi_cosimulation_tclcmds('vsimmatlabsysobj'));
  case 'Xcelium'
      nclaunch('tclstart',viterbi_cosimulation_tclcmds('hdlsimmatlabsysobj'));
end
Timeout=30;
processid = pingHdlSim(Timeout);
Check if HDL simulator is ready for Cosimulation.
assert(ischar(processid),['Timeout: HDL simulator took more than ', num2str(Timeout),' seconds to setup,please increase the timeout in ''pingHdlSim''']);
disp('...Simulator is ready for cosimulation.');

For Vivado Simulator

1. To generate the HDL cosimulation System object by using the Cosimulation Wizard, follow up to step 6 mentioned in the Cosimulation Wizard for MATLAB System Object.

On the Input/Output Ports page, perform the following steps.

a. Set the clk Port Name to Clock.

b. Set the reset and clk_enable Port Name to Reset.

c. Set the In1 and In2 Port Name to Input.

d. Set the ce_out Port Name to Unused.

e. Set the Out1 Port Name to Output.

f. Click Next.

On the Output Port Details, perform the following steps.

a. Set Sample Time to 10.

b. Set Sign to Unsigned.

c. Set fraction length to 0.

d. Click Next.

On the Clock/Reset Details page perform the following steps.

a. Set the clock period to 10.

b. Set the reset Initial Value to 1 and Duration to 8.

c. Set the clk_enable Initial Value to 0 and Duration to 1.

d. Click Next.

On the Start Time Alignment page, perform the following steps.

a. Set the Pre Run Time by setting HDL time to start cosimulation to 0.

b. Click Update Diagram.

c. Click Next.

On the System Obj. Generation page set HDL simulator sampling period to 10 and click Finish.

2. Generated System object script should look as follows.

xsiData = createXsiData( ...
   'design', 'xsim.dir/design/xsimk', ...
   'lang', 'vhdl', ...
   'prec', '1ps', ...
   'types', {'Logic' 'Logic' 'Logic' }, ...
   'dims', {3 3 1 }  ...
  );

obj = hdlcosim( ...
   'HDLSimulator', 'Vivado Simulator', ...
   'InputSignals', {'/viterbi_block/In1','/viterbi_block/In2'}, ...
   'OutputSignals', {'/viterbi_block/Out1'}, ...
   'OutputSigned', [false], ...
   'OutputDataTypes', {'fixedpoint'}, ...
   'OutputFractionLengths', [0], ...
   'ClockResetSignals', {'/viterbi_block/clk' '/viterbi_block/reset' '/viterbi_block/clk_enable' }, ...
   'ClockResetTypes', {'Active Rising Edge Clock' 'Step 1 to 0' 'Step 0 to 1' }, ...
   'ClockResetTimes', {{10,'ps'} {8,'ps'} {1,'ps'} }, ...
   'PreRunTime', {0,'ps'}, ...
   'SampleTime', {10,'ps'}, ...
   'XSIData', xsiData  ...
  );

3. Assign the System object to a new variable hDec by using this command in MATLAB.

hDec = hdlcosim_viterbi_block;

Run Cosimulation

This example simulates the BPSK communication system in MATLAB incorporating the Viterbi decoder HDL implementation via the cosimulation System object. This section of the code calls the processing loop to process the data frame-by-frame with 1024 bits in each data frame.

for counter = 1:20480/FrameSize
  data            = randi([0 1],FrameSize,1);
  encodedData     = hConEnc(data);
  modSignal       = hMod(encodedData);
  receivedSignal  = hChan(modSignal);
  demodSignalSD   = hDemod(receivedSignal);
  quantizedValue  = fi(4-demodSignalSD,0,3,0);
  input1          = quantizedValue(1:2:2*FrameSize);
  input2          = quantizedValue(2:2:2*FrameSize);

   receivedBits    = hDec(input1, input2);
   errors          = hError(data, double(receivedBits));
 end

Display Bit Error Rate

The bit error rate is displayed for the Viterbi decoder.

sprintf('Bit Error Rate is %d\n',errors(1))

Destroy Cosimulation System Object to Release HDL Simulator

The HDL simulator is unblocked when the HDL cosimulation System object is destroyed in MATLAB. Close the HDL simulator session manually.

clear hDec;

See Also