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Troubleshooting FIL

If you get a message or error at any time during the FIL process (from generating the FIL block to running the simulation), consult one of the following tables for a possible reason and solution.

Message or ErrorReasonFix
Design does not meet timing goals (this message is generated from the FPGA design software)The design does not meet timing goals and the software was unable to create the programming file.Change some part of your design or use a different development board.
Failed to load bitstreamThe default libusb shipped with the Debian® client is not compatible with iMPACT™.Consult Xilinx® user documentation for Linux® distribution compatibility of ISE tools.
RAM in design does not match up to Simulink® RAM after first simulation runSimulink starts from time 0 every time, which means the RAM in Simulink is initialized to zero. However, this is not true in hardware. If you have RAM in your design, the first simulation will match Simulink, but any subsequent runs may not match.

The workaround is to reload the FPGA before re-running the simulation.

Did not receive data from attached hardware (Ethernet connection)The connectivity between the host and FPGA development board was lost during the simulation. This error could be caused by a bad network interface card (NIC), bad cable, or loss of power. It also could be caused by an issue with the operating system IP stack where the IP address / MAC address binding is being refreshed, interfering with the transmission of data from the development board to the host.

Check the cables and power so that connectivity can be re-established.

You can avoid the IP address / MAC address refresh issue by setting a static entry in the ARP cache (the table that holds the address bindings). You will need to gather the IP address and MAC address by examining the Hardware Information section of the FIL block mask. The following examples will assume the default values of 192.168.0.2 for the IP address and 00-0A-35-02-21-8A for the MAC address.

For Windows®: With system administrator privileges, execute the following in a command shell:

cmd> arp -s 192.168.0.2 00-0A-35-02-21-8A

To confirm that the operation outcome was as you expected, examine the table and verify the output shows a static entry type:

  cmd> arp -a 192.168.0.2

Interface: 192.168.0.8 --- 0x16
Internet Address      Physical Address      Type
192.168.0.2           00-0a-35-02-21-8a     static

For Linux: As root or via "sudo" privileges, execute the following in a command shell (note that the MAC address delimiter is ":" instead of "-"):

sh> sudo /usr/sbin/arp -s 192.168.0.2 00:0A:35:02:21:8A

To confirm the operation outcome was as you expected, examine the table and verify the output shows a static entry type (so noted by the PERM string):

sh> sudo /usr/sbin/arp -a 192.168.0.2
       
? (192.168.0.2) at 00:0a:35:02:21:8a [ether] PERM on eth3
Did not receive data from attached hardware (design frequency)The configured frequency is too high or too low for the FIL hardware design.

Configure the frequency of your design to the default 25MHz, and rebuild the design, using one of the following workflows:

  1. If using filWizard: In the FIL Options section, set Advanced Options > FPGA system clock frequency (MHz), to 25. Click Next, and continue with the remaining steps to build your design. See FPGA-in-the-Loop Wizard for more details.

  2. If using HDL Workflow Advisor: In step 1.2, set Target Frequency (MHz) to 25. Click Run This Task, and continue with the remaining steps to build your design. See FIL Simulation with HDL Workflow Advisor for Simulink for more details.

Failed to load shared library sld_hapi.dll (JTAG connection)

The Altera® Quartus® II executables are not on the system path.

Put the Altera Quartus II executables on the system path. If using Linux, make sure that the Quartus II library is on LD_LIBRARY_PATH before you start MATLAB®

Failed to load shared library libsld_hapi_dll_loader.so (JTAG connection)

Two possible reasons:

  • The version of Altera Quartus II on the host computer is not supported.

  • The Altera Quartus II executables are not on the system path.

  • Make sure you are using Altera Quartus II version 13.1 or higher on the host computer.

  • Make sure that the Quartus II library is on LD_LIBRARY_PATH before you start MATLAB

Cannot load any more object with static TLS

There is a finite number of libraries with TLS initialization that can be loaded for a given process. Ensure the Altera Quartus II library has priority.

Add your location of Altera/15.0-mw-0/Linux/quartus/linux64/libjtag_client.so to LD_PRELOAD. Then restart MATLAB.

Undefined reference to lzma_code@XZ_5.0 (JTAG connection)The Quartus II library liblzma.so.5 has over-shadowed the Linux distribution version of liblzma.so.5.Prepend the Linux distribution library path before the Quartus II library on LD_LIBRARY_PATH. For example, /lib/x86_64-linux-gnu:$QUARTUS_PATH.
Unable to find the JTAG communication cable attached to the host computer (JTAG connection)JTAG cable is not connected. It is also possible that the JTAG cable is defective.Use the JTAG download cable to connect the FPGA development board with the computer.
Failed to open SLD hub (JTAG connection)The SLD hub is missing. It is required for FPGA-in-the-loop simulation with the Altera JTAG cable.Make sure that the FPGA is programmed with the correct programming file, which contains the SLD hub.
Reset pin not connected to RESET push button
(Alternate message: "Did not get version" displayed in the cosim block)
Most likely scenario is that you changed the Ethernet card but did not re-program the FPGA, although other reasons may be also possible.Use the FPGA Board Manager to see if there is a reset pin specified for the custom or built-in board. If there is a reset pin specified, look at the board specification manual to see which push button it is connected to.