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Automatic Verification of Generated HDL Code from Simulink

The automatic verification feature integrates verification as part of the workflow for HDL cosimulation using the HDL Workflow Advisor. During this workflow, Simulink® generates a testbench model for HDL cosimulation. This testbench model compares the generated HDL DUT outputs (from the HDL Cosimulation block) with the original Simulink block outputs. This step automatically runs this testbench and returns pass/fail information. If the outputs of the HDL DUT match the output of original Simulink block in the testbench, the test passes.

This feature requires an HDL Coder™ and an HDL Verifier™ license.

  1. To open HDL Workflow Advisor for your model, select the APPS tab on the Simulink toolstrip, and select HDL Coder (HDL Coder). Then, click the Workflow Advisor button.

  2. Step 1.1, select Generic ASIC/FPGA.

  3. Run all steps under 2, Prepare Model For HDL Code Generation.

  4. At step 3.1, Set HDL Options, click HDL Code Generation Settings to open the configuration parameters on the HDL Code Generation pane.

  5. Set the HDL language, and under Test Bench select Cosimulation model. Then set Simulation tool to Mentor Graphics ModelSim, Cadence Incisive, or Xilinx Vivado Simulator for your HDL simulator. Click OK to return to the HDL Workflow Advisor window.

  6. At Step 3.2, Generate RTL Code and Testbench, select Generate test bench. This selection causes Step 3.3 to appear. Click Run This Task to generate the RTL code and testbench.

  7. At step 3.3, click Run This Task. The HDL Workflow Advisor and HDL Verifier verify the generated HDL using cosimulation between the HDL Simulator and the Simulink testbench. Any relevant status messages are displayed in the status window in the HDL Workflow Advisor.