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Assign clock ports to cosimulation block or System object

Since R2022b


    specifyClock(cosimConfigObj,name) explicitly maps the HDL port named name as a clock port in the generated block or System object™. The attributes for the clock inherit default values from the default_clock_definition row of the ClockPorts table.

    specifyClock(__ ,Name=Value) sets properties using one or more name-value arguments in addition to the input arguments in the previous syntax. Unspecified arguments inherit the value from 'default_clock_definition'.

    To change the default clock attributes, specify values for the 'default_clock_definition’.

    specifyClock(__ ,name,[]) clears the definition for the clock port (or ports) specified in name. For example: specifyClock(c,'clk',[]) clears the definition for the clock named clk in the ClockPorts table.

    Input Arguments

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    Cosimulation configuration, specified as a cosimulationConfiguration object.

    Name of the HDL port to map as a clock port in the generated HDL Cosimulation block or hdlverifier.HDLCosimulation System object, specified as a string or a character vector. For multiple clocks, specify a cell array of port names.

    Example: clk

    Example: {'clk1','clk2','clk3'}

    Data Types: char | string

    Name-Value Arguments

    Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

    Example: specifyClock(c,'clk1',Period=30) assigns the port named clk1 a period of 30 time units as defined by HDLTimeUnit.

    Active clock edge, specified as Rising or Falling.

    Clock period, specified as a positive integer of HDLTimeUnit units.

    Version History

    Introduced in R2022b