displayTriggerCondition

Display overall trigger condition

Syntax

displayTriggerCondition(DC)

displayTriggerCondition(DC,N)

Description

Add-On Required: This feature requires one of these add-ons.

• HDL Verifier Support Package for Intel FPGA Boards
• HDL Verifier Support Package for AMD FPGA and SoC Devices

displayTriggerCondition(DC) displays the signal value comparisons and logical operator that define the overall trigger condition in trigger stage 1. DC is a customized data capture object.

displayTriggerCondition(DC,N) displays the signal value comparisons and logical operator that define the overall trigger condition in a trigger stage specified by N. DC is a customized data capture object.

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

N — Trigger stage

integer from 1 to M

Trigger stage, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. Use N to display the trigger condition in Nth trigger stage. If you do not specify N, by default, the function displays the trigger condition in trigger stage 1.

Version History

Introduced in R2017a