Distributed Pipelining and Clock-Rate Pipelining Guidelines
The code generator introduces registers when you specify certain block implementations or use certain settings. You can follow these guidelines to learn more about these registers and how you can use them to optimize the timing of your design.
Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.
Clock-Rate Pipelining Guidelines
In most cases, the code generator introduces the registers in regions that run slower than the clock rate. To avoid or minimize additional latency, you can run these registers at the fast clock rate by using clock-rate pipelining. You can use clock-rate pipelining with these optimizations:
Input and output pipelining
Multi-cycle block implementations, such as complex math operations like Sqrt and Reciprocal.
Floating-point library mapping
Resource sharing and streaming
For designs with multiple hierarchies, when you want to perform certain system-level optimizations, such as sharing or distributed pipelining, it is recommended that you have the HDL block property FlattenHierarchy enabled on the top-level Subsystem.
To learn more about clock-rate pipelining and blocks that act as barriers to this optimization, see Clock-Rate Pipelining.
Recommended Distributed Pipelining Settings
Distributed pipelining is a speed optimization that reduces the critical path by moving existing delays in your design while preserving the functional behavior. This optimization moves the delays within a subsystem while preserving the hierarchy.
To use this optimization for a design, in the Configuration Parameters dialog box, on the HDL Code Generation > Optimization pane, navigate to the Pipelining tab and select the Distributed pipelining check box.
To more effectively use this optimization, in the Configuration Parameters dialog box, on the HDL Code Generation > Optimization pane, you can specify these additional settings.
ConstrainedOutputPipeline: Make sure that the total number of delays that are inserted including any input and output pipelining that you specify is greater than or equal to the value that you specify for ConstrainedOutputPipeline on the Subsystem.
Use synthesis estimates for distributed pipelining: Select this option if you want to use synthesis timing estimates to calculate the propagation delays of the components in your design for distributed pipelining. This option can more accurately reflect how components function on hardware to better distribute pipelines in your design and maximize the clock frequency for your target device. See Distributed Pipelining Using Synthesis Timing Estimates.
Clock-rate pipelining: Select this option if you want the code generator to insert registers at the clock rate instead of the data rate.
Allow clock-rate pipelining of DUT output ports: Select this option if you want the code generator to insert registers at the clock rate instead of the data rate at the DUT output ports.
Allow design delay distribution: Disable this option if you do not want the code generator to move the delays you added to your design. The optimization only moves pipeline registers.
Pipeline distribution priority: Specify whether you want the priority to be
Performance. If you use
Performance, make sure that the simulation results match. In some cases, this setting moves registers into blocks that have initial values such as constants, which can affect simulation results.
The subsystem to which you apply the optimization must meet these requirements:
The subsystem that you apply this optimization on cannot contain any feedback loops.
The subsystem must include only blocks that are supported for distributed pipelining. For a list of unsupported blocks, see Limitations of Distributed Pipelining. As a workaround:
Place some of the unsupported blocks, such as Dot Product blocks, inside another subsystem that does not have distributed pipelining enabled.
Change the Pipeline distribution priority parameter to
Performancefor blocks such as Enabled Subsystem blocks.
The Sample Time parameter of the blocks must be discrete. If you have blocks with Sample Time set to
inf, change them to
-1if the infinite sample time propagates to the DUT output. To identify and change the sample time programmatically, see Change Block Parameters by Using find_system and set_param.