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Force clock enable

Specify whether the test bench forces clock enable input signals

Model Configuration Pane: Test Bench


Specify whether the test bench forces clock enable input signals.


This property enables the Clock enable delay (in clock cycles) option.

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.


On (default) | Off

The test bench forces the clock enable input signals to active-high (1) or active-low (0), depending on the setting of the clock enable input value.


A user-defined external source forces the clock enable input signals.


To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
                'ForceClockEnable', 'off')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'ForceClockEnable', 'off')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: ForceClockEnable
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2012a