Programmatically Generate, Verify, and Synthesize HDL Code from MATLAB Code

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This example shows how to programmatically perform floating-point to fixed-point conversion, generate HDL code, verify the generated HDL code with an HDL test bench, and synthesize the generated HDL code by using the command-line interface.

This example uses ModelSim® as the HDL simulation tool and Xilinx® Vivado® as the third-party synthesis tool.

To generate HDL code and perform FPGA synthesis by using the MATLAB HDL Workflow Advisor, see Generate and Synthesize HDL Code for Symmetric FIR Filter Using the HDL Workflow Advisor.

This example implements a discrete-time integrator and its test bench. The discrete-time integrator algorithm uses the Forward Euler method to integrate an input signal over time.

Set Up the Third-Party Synthesis Tool and HDL Simulator

First, set up your third-party synthesis tool and HDL simulator. For a list of the supported versions for third-party tools, see HDL Language Support and Supported Third-Party Tools and Hardware.

This example uses Xilinx Vivado. To set the path to the third-party synthesis tool, use the function hdlsetuptoolpath. In the MATLAB Command Window, use this command, and replace the path with your installation path:

hdlsetuptoolpath("ToolName","Xilinx Vivado","ToolPath",vivadopath);

To check your Xilinx Vivado synthesis tool setup, launch Xilinx Vivado by running this command:

!vivado

To simulate the generated HDL code using an HDL test bench, use an HDL simulator, such as ModelSim®. For more information on setting up third-party FPGA synthesis tools and HDL simulators, see Set Up Tools.

Note

Do not use spaces in file names or paths to prevent FPGA synthesis failures. You can use the workDir name-value argument of the openExample function to open this example in a directory with a shorter name and no spaces or special characters. For example, this code sets the current working directory as your temporary folder directory for your system and opens the example.

tempdir
openExample("hdlcoder/GenerateHDLFromMATLABUsingTheCommandLineInterfaceExample",workDir=tempdir)

Create a Fixed-Point Conversion Configuration Object

Next, set up floating-point to fixed-point conversion by using a coder.FixPtConfig configuration object. If your MATLAB design already uses fixed-point data types and functions, skip this step.

In this example, the MATLAB design is mlhdlc_dti, and the test bench is mlhdlc_dti_tb. Create a coder.FixPtConfig configuration object with default settings and set the TestBenchName property to mlhdlc_dti_tb.

close all;
clear mlhdlc_dti

fixptcfg = coder.config("fixpt");
fixptcfg.TestBenchName = "mlhdlc_dti_tb";

HDL Coder proposes fixed-point types based on your choice of either word length or fraction length. These two options are mutually exclusive. For this example, base the fixed-point data types on a word length of 24. Set DefaultWordLength to 24 and ProposeFractionLengthsForDefaultWordLength to true.

fixptcfg.DefaultWordLength = 24;
fixptcfg.ProposeFractionLengthsForDefaultWordLength = true;

Alternatively, you can base the fixed-point types on fraction length. For example, this code configures the fixpt configuration object to propose types based on a fraction length of 10:

fixptcfg.DefaultFractionLength = 10;
fixptcfg.ProposeWordLengthsForDefaultFractionLength = true;

Set the safety margin percentage. HDL Coder increases the simulation data range on which it bases the fixed-point data type proposal by the safety margin percentage. For example, the default safety margin is 4, which increases the simulation data range used for fixed-point type proposal by 4%. For this example, set SafetyMargin to 10.

fixptcfg.SafetyMargin = 10;

Set the LaunchNumericTypesReport property to true. When this setting is enabled, HDL Coder generates a numeric types report when you generate HDL code.

fixptcfg.LaunchNumericTypesReport = true;

Create an HDL Configuration Object

Create a coder.HdlConfig configuration object and set the TestBenchName to mlhdlc_dti_tb.

hdlcfg = coder.config("hdl");
hdlcfg.TestBenchName = "mlhdlc_dti_tb";

You can generate VHDL, Verilog, or SystemVerilog HDL code. HDL Coder generates VHDL code by default. To generate Verilog code, set the TargetLanguage property to Verilog:

hdlcfg.TargetLanguage = "Verilog";

You can also generate SystemC and SynthesizableC++ High-Level Synthesis (HLS) code from MATLAB designs. To programmatically generate HLS code from a MATLAB design, see Get Started with MATLAB to High-Level Synthesis Workflow Using the Command Line Interface.

Define clear timing boundaries for static timing analysis. To ensure register-to-register timing paths, add an input and output pipeline at the design interface. Set InputPipeline and OutputPipeline to 1.

hdlcfg.InputPipeline = 1;
hdlcfg.OutputPipeline = 1;

To optimize your design, enable DistributedPipelining.

hdlcfg.DistributedPipelining = true;

To learn more about distributed pipelining, see Specify Distributed Pipelining Settings.

To verify the generated Verilog code in a third-party HDL simulator, you must set up the HDL configuration object for your target simulator. In this example, you simulate the generated HDL code in ModelSim.

To enable HDL simulation, set the SimulateGeneratedCode property to true.

hdlcfg.SimulateGeneratedCode = true;

To generate an HDL test bench, set the GenerateHDLTestBench property to true.

hdlcfg.GenerateHDLTestBench = true;

To use ModelSim as the third-party HDL simulator, set the SimulationTool property to ModelSim.

hdlcfg.SimulationTool = "ModelSim";

Next, enable FPGA synthesis and implementation and specify your target synthesis platform in the HDL configuration object. For this example, you specify Xilinx Vivado as the synthesis tool.

To enable FPGA synthesis and implementation, set the SynthesizeGeneratedCode and PlaceAndRoute properties to true.

hdlcfg.SynthesizeGeneratedCode = true;
hdlcfg.PlaceAndRoute = true;

Specify the third-party synthesis tool. This example uses Xilinx Vivado.

hdlcfg.SynthesisTool = "Xilinx Vivado";

Specify a target device and frequency. This example targets an AMD Virtex 7 FPGA.

hdlcfg.SynthesisToolChipFamily = "Virtex7";
hdlcfg.SynthesisToolDeviceName = "xc7vh580t";
hdlcfg.SynthesisToolPackageName = "hcg1155";
hdlcfg.SynthesisToolSpeedValue = "-2G";
hdlcfg.TargetFrequency = 200;

Generate, Verify, Synthesize, and Implement HDL Code

Use the codegen command to convert floating-point data types to fixed-point, generate HDL code, generate an HDL test bench, and facilitate FPGA synthesis and implementation. To convert floating-point to fixed-point data types, use the -float2fixed option and specify the coder.FixptConfig object. To use your HDL configuration, use the -config option and the coder.HdlConfig object. Finally, include the function name, mlhdlc_dti.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_dti

===================================================
Design Name: <a href="matlab:edit('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/mlhdlc_dti.m')">mlhdlc_dti</a>
Test Bench Name: <a href="matlab:edit('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/mlhdlc_dti_tb.m')">mlhdlc_dti_tb</a>
===================================================

Input types not specified for design(s) 'mlhdlc_dti', inferring types by simulating the first test bench: 'mlhdlc_dti_tb' in the base workspace.

============= Step1: Analyze Floating-Point Code ==============

Code generation successful.



============= Step1a: Verify Floating-Point Code ==============

### Analyzing the design 'mlhdlc_dti'
### Analyzing the test bench(es) 'mlhdlc_dti_tb'
### Begin Floating-Point Simulation (Instrumented)
### Floating-Point Simulation Completed in   2.8252 sec(s)
### Elapsed Time:             3.6860 sec(s)

============= Step2: Propose Types Based on Range Information ==============


============= Step3: Generate Fixed-Point Code ==============

### Generating Fixed-Point MATLAB Code <a href="matlab:edit('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/fixpt/mlhdlc_dti_fixpt.m')">mlhdlc_dti_fixpt</a> Using Proposed Types
### Generating Fixed-Point MATLAB Design Wrapper <a href="matlab:edit('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/fixpt/mlhdlc_dti_wrapper_fixpt.m')">mlhdlc_dti_wrapper_fixpt</a>
### Generating Mex file for ' mlhdlc_dti_wrapper_fixpt '
Code generation successful: <a href="matlab: emlcprivate('emcOpenReport','/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/fixpt/reports/mlhdlc_dti_wrapper_fixpt_mex/html/report.mldatx');">View report</a>
### Generating Type Proposal Report for 'mlhdlc_dti' <a href="matlab:web('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/fixpt/mlhdlc_dti_report.html', '-new')">mlhdlc_dti_report.html</a>

===================================================
Code generation successful.

### Begin MATLAB to HDL Code Generation...
### Working on DUT: mlhdlc_dti_fixpt.
### Using TestBench: mlhdlc_dti_tb.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 2 cycles.
### Output port 2: 2 cycles.
### Begin Verilog Code Generation
### Working on mlhdlc_dti_fixpt as <a href="matlab:edit('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/hdlsrc/mlhdlc_dti_fixpt.v')">mlhdlc_dti_fixpt.v</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating Optimization report  
### To rerun codegen evaluate the following commands...

---------------------
cgi    = load('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/hdlsrc/codegen_info.mat');
cfg    = cgi.CodeGenInfo.codegenSettings;
fxpCfg = cgi.CodeGenInfo.fxpCfg;
codegen -float2fixed fxpCfg -config cfg -report
---------------------

### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc26a_3146167_3707834/tpe4ad3335/hdlcoder-ex02255591/codegen/mlhdlc_dti/hdlsrc/mlhdlc_dti_fixpt_hdl_conformance_report.html')">mlhdlc_dti_fixpt_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: To view the report, open('codegen/mlhdlc_dti/hdlsrc/html/report.mldatx')

After you run the codegen command, use the numeric types report to review word and fraction lengths. In the MATLAB Command Window, in Step 3 of the codegen output, click the mlhdlc_dti_report.html link to view the numeric types report.

Open the HDL code generation report. Click the View report link to open the HDL code generation report in the HDL Coder Report Viewer. For more information on HDL code generation reports, see Code Generation Reports.

FPGA synthesis and implementation generate area and timing reports for your design based on the target device. If you enable FPGA synthesis and implementation, in the MATLAB Command Window, in the codegen output, click the post_synth_report.html link to open the post synthesis report.

See Also

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