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Feeds
답변 있음
How to give random inputs for my simulink design?
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) an...
How to give random inputs for my simulink design?
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) an...
2일 전 | 0
답변 있음
Convert Simulink to m file
Correction in the above thread / Accepted Ansswer. Simulink Coder and embedded Coder products support C, C++ code generation...
Convert Simulink to m file
Correction in the above thread / Accepted Ansswer. Simulink Coder and embedded Coder products support C, C++ code generation...
2일 전 | 0
답변 있음
FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html To target FPGA and SoC devices, use the IP...
FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html To target FPGA and SoC devices, use the IP...
2일 전 | 0
답변 있음
MATLAB Function always infers outputs as doubles
It would be hard to reproduce with the partial information above. Sharing a sample MATLAB function supported syntax for HDL cod...
MATLAB Function always infers outputs as doubles
It would be hard to reproduce with the partial information above. Sharing a sample MATLAB function supported syntax for HDL cod...
2일 전 | 0
답변 있음
HOW TO: Object detection using automotive RADAR
You should explore HDL Coder based examples in these two products Deep Learning HDL Toolbox: https://www.mathworks.com/help/dee...
HOW TO: Object detection using automotive RADAR
You should explore HDL Coder based examples in these two products Deep Learning HDL Toolbox: https://www.mathworks.com/help/dee...
3일 전 | 0
답변 있음
Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]
For sobel filter examples using HDL Coder from Simulink consider reviewing these examples. (sampleIn and sampleOut DUT) https:...
Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]
For sobel filter examples using HDL Coder from Simulink consider reviewing these examples. (sampleIn and sampleOut DUT) https:...
8일 전 | 0
답변 있음
I am trying to use "Deploy Neural Network Regression Model to FPGA/ASIC Platform" example
https://www.mathworks.com/matlabcentral/answers/2102651-i-am-trying-to-use-deploy-neural-network-regression-model-to-fpga-asic-p...
I am trying to use "Deploy Neural Network Regression Model to FPGA/ASIC Platform" example
https://www.mathworks.com/matlabcentral/answers/2102651-i-am-trying-to-use-deploy-neural-network-regression-model-to-fpga-asic-p...
15일 전 | 0
답변 있음
How can HDL Code Generation for a full system be performed with System Composer Model that contains multiple Simulink models?
Hi Brad, can you create a support request to help further address this issue? We can followup offline on how to connect System ...
How can HDL Code Generation for a full system be performed with System Composer Model that contains multiple Simulink models?
Hi Brad, can you create a support request to help further address this issue? We can followup offline on how to connect System ...
28일 전 | 1
| 수락됨
답변 있음
Implementing logarithmic function via Simulink HDL Coder
Can you share a bit more about your application and requirements for log? These results can be generated based on your target...
Implementing logarithmic function via Simulink HDL Coder
Can you share a bit more about your application and requirements for log? These results can be generated based on your target...
29일 전 | 0
답변 있음
Difference of sine waveform in simulink and real-time
You may find this workflow useful: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simscape-model.html >> whi...
Difference of sine waveform in simulink and real-time
You may find this workflow useful: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simscape-model.html >> whi...
29일 전 | 0
답변 있음
Confused between Hardware to perform Inference
You can follow this example to see how to customize the generated DL Processor with HDL Coder. https://www.mathworks.com/help/d...
Confused between Hardware to perform Inference
You can follow this example to see how to customize the generated DL Processor with HDL Coder. https://www.mathworks.com/help/d...
30일 전 | 1
| 수락됨
답변 있음
HDL Coder compatibility issue with Libero SoC 2023.2
It looks like you are using MATLAB R2023b and Libero 2023.2. Please confirm. As per HDL Coder supported versions, you need to...
HDL Coder compatibility issue with Libero SoC 2023.2
It looks like you are using MATLAB R2023b and Libero 2023.2. Please confirm. As per HDL Coder supported versions, you need to...
대략 1개월 전 | 0
답변 있음
Loop based error while performing HDL conversion using HDL workflow
Your MATLAB Coding style is incompatible with MATLAB to HDL workflow. Here are few general pointers while we respond to your spe...
Loop based error while performing HDL conversion using HDL workflow
Your MATLAB Coding style is incompatible with MATLAB to HDL workflow. Here are few general pointers while we respond to your spe...
대략 1개월 전 | 0
답변 있음
Resources utilization for generated HDL code
Please find the attached slides that show how to generate the FPGA Synthesis report from a Simulink model using HDL Coder.
Resources utilization for generated HDL code
Please find the attached slides that show how to generate the FPGA Synthesis report from a Simulink model using HDL Coder.
대략 2개월 전 | 0
| 수락됨
답변 있음
Resources utilization for generated HDL code
This is an estimation report from HDL Coder. >> makehdl('sfir_fixed/symmetric_fir') ### Working on the model sfir_fixe...
Resources utilization for generated HDL code
This is an estimation report from HDL Coder. >> makehdl('sfir_fixed/symmetric_fir') ### Working on the model sfir_fixe...
대략 2개월 전 | 0
답변 있음
Dataflow Conversion Error when generating hdl code from simulink
This is an unexpected error and seems related to this bug report. https://www.mathworks.com/support/bugreports/3054173
Dataflow Conversion Error when generating hdl code from simulink
This is an unexpected error and seems related to this bug report. https://www.mathworks.com/support/bugreports/3054173
대략 2개월 전 | 0
답변 있음
Is there anyway to test custom IP cores on MATLAB/SIMULINK
You can make a DUT with Simulink subsystems and combine them with your custom IP using Black box interface and the combined IP c...
Is there anyway to test custom IP cores on MATLAB/SIMULINK
You can make a DUT with Simulink subsystems and combine them with your custom IP using Black box interface and the combined IP c...
대략 2개월 전 | 0
답변 있음
IP core generation for built-in Simulink model
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to suppo...
IP core generation for built-in Simulink model
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to suppo...
2개월 전 | 0
답변 있음
is there a way to define 'fixdt' in a Matlab script and use this variable in a Simulink User-Defined Function?
Can you share a bit more details of this usecase? A sample model would be helpful. Are you using this in the context of a MATL...
is there a way to define 'fixdt' in a Matlab script and use this variable in a Simulink User-Defined Function?
Can you share a bit more details of this usecase? A sample model would be helpful. Are you using this in the context of a MATL...
2개월 전 | 0
| 수락됨
답변 있음
Trouble with Vitis Model Composer 2023.2! MATLAB R2021b crashes when I want to open the Model Composer Hub component.
This might be related to a known MATLAB issue: https://www.mathworks.com/matlabcentral/answers/364551-why-is-matlab-unable-to...
Trouble with Vitis Model Composer 2023.2! MATLAB R2021b crashes when I want to open the Model Composer Hub component.
This might be related to a known MATLAB issue: https://www.mathworks.com/matlabcentral/answers/364551-why-is-matlab-unable-to...
2개월 전 | 0
답변 있음
IP core generation for built-in Simulink model
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant desi...
IP core generation for built-in Simulink model
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant desi...
3개월 전 | 0
답변 있음
what is the difference between FPGA Turnkey and IP Core Generation?
Targeting FPGA & SoC Hardware with HDL Coder Workflow Design a system that you can deploy on hardware or a combination of h...
what is the difference between FPGA Turnkey and IP Core Generation?
Targeting FPGA & SoC Hardware with HDL Coder Workflow Design a system that you can deploy on hardware or a combination of h...
3개월 전 | 0
답변 있음
Force MATLAB code to run on hardware
Please share your code / model that you want to generate HDL from. if you are taking the ML/DL route, please consider https://w...
Force MATLAB code to run on hardware
Please share your code / model that you want to generate HDL from. if you are taking the ML/DL route, please consider https://w...
3개월 전 | 0
답변 있음
How to create a simulink model for testbench
You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model >> makehdl('l...
How to create a simulink model for testbench
You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model >> makehdl('l...
3개월 전 | 0
답변 있음
Error while generating HDL code from Simulink for Canny Edge Detection
For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be ou...
Error while generating HDL code from Simulink for Canny Edge Detection
For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be ou...
3개월 전 | 0
| 수락됨
답변 있음
HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()
The error message is not expected. Can you share your model? Either HDL Coder needs to generate code from the model or generate ...
HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()
The error message is not expected. Can you share your model? Either HDL Coder needs to generate code from the model or generate ...
3개월 전 | 0
| 수락됨
답변 있음
How to get the stored integer representation of a single-precision floating point in simulink (HDL Coder)?
https://www.mathworks.com/help/hdlcoder/ref/floattypecast.html Float Typecast Typecast a floating-point type to an unsigned in...
How to get the stored integer representation of a single-precision floating point in simulink (HDL Coder)?
https://www.mathworks.com/help/hdlcoder/ref/floattypecast.html Float Typecast Typecast a floating-point type to an unsigned in...
3개월 전 | 1
| 수락됨
답변 있음
wait statement without UNTIL clause not supported for synthesis Error when using HDL coder
Please reach out to tech support if this issue is still reproducible. % Copy the AES demo files to a temporary folder mlhdlc_d...
wait statement without UNTIL clause not supported for synthesis Error when using HDL coder
Please reach out to tech support if this issue is still reproducible. % Copy the AES demo files to a temporary folder mlhdlc_d...
4개월 전 | 0
답변 있음
Matlab code generation and support for Xilinx Cora Z7-07S
HDL Coder doesn't have explicit support for this board, but the closest board that we support looks to be the ZedBoard or ZC702....
Matlab code generation and support for Xilinx Cora Z7-07S
HDL Coder doesn't have explicit support for this board, but the closest board that we support looks to be the ZedBoard or ZC702....
4개월 전 | 0
답변 있음
SystemC code generation directly from SIMULINK model
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workfl...
SystemC code generation directly from SIMULINK model
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workfl...
4개월 전 | 0
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