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How to use FFT HDL Optimized ?
You seem to be generating the HDL code for the entire model. Please select just the subsystem to generate HDL code.

11년 초과 전 | 0

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Cyclic Prefix Removal OFDM FFT IEEE802.11
I have modified it to use the workspace for data and valid in. valid in now is high for 64, low for 16, high for 64 and low for ...

11년 초과 전 | 0

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Cyclic Prefix Removal OFDM FFT IEEE802.11
Can you post a simpler version of your model for me to take a look at? In R2014a, there is no option for natural order output. ...

11년 초과 전 | 0

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Cyclic Prefix Removal OFDM FFT IEEE802.11
The method to skip those samples depends on the FFT block you are using. The HDL FFT blocks have a valid or frame start input, w...

거의 12년 전 | 0

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How to use FFT HDL Optimized ?
There is an example in HDL Coder "OFDM Receiver with 512-Point Streaming I/O FFT" that uses the FFT HDL Optimized block. Are you...

거의 12년 전 | 0

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Sampling rate in Simulink model and HDL coder
The base clock period is determined from the rates you put in Simulink. If you model only using the rates that are multiples of ...

거의 12년 전 | 1

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Block to assign initial value for internal signal compatible with HDL coder?
If you use the Delay block, you can assign an initial value which HDL Coder uses. Your model will look as follows: Delay block...

거의 12년 전 | 0

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In Simulink ,the pn sequence generator(essential blk) in frame based mode s not being accepted by the hdl converter. But the output of the pn sequence generator is given to a serial to parallel converter. What cud b the alternative for this?
Please check to see if the inputs are constants. If so, change the sample time on the constant block to be 1 or some such value....

거의 12년 전 | 0

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Unavailability of frame based processing in HDL coder
You will have to convert your model to a sample based version. Even in the sample based version, you can have access to more tha...

거의 12년 전 | 0

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Data overshoot in FPGA implementation
Where are you seeing these overshoots? Is it during transmission with an RF transmitter? One suggestion is to try to loop back t...

대략 12년 전 | 0

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What is the Fixed-Point function replacement for atan?
You can also try using cordicatan2, which gives you a CORDIC based inverse tangent value.

대략 12년 전 | 1

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HDL cosimulation output different from FPGA output
To debug this, I suggest a few things: 1. Run the HDL code and the testbench in ModelSim to see if it passes. This will confi...

대략 12년 전 | 0

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whether any .m file consists of MATLAB function of a transceiver program can be converted into its HDL code for FPGA implementation ? If yes then anyone can please guide me on that?
In order to use the modulator and demodulator, you will need to use the System objects (for example: comm.QPSKModulator). A numb...

대략 12년 전 | 0

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Can a Verilog RTL be simulated using Matlab Testbench?
You can cosimulate Verilog code with MATLAB or Simulink. There are examples provided in the <http://www.mathworks.com/help/hdlve...

대략 12년 전 | 1

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streaming HDL friendly FFT works in Simulink, not in ModelSim
Is it possible for you to contact technical support at MathWorks with this model? If you generate the HDL code and testbench fr...

대략 12년 전 | 0

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streaming HDL friendly FFT works in Simulink, not in ModelSim
Have you tried generating the co-simulation model with HDL Coder? That co-simulation model takes the data from Simulink, runs it...

대략 12년 전 | 0

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Regarding configuremodelsim, It does not configure the selected modelsim
You can call the MATLAB function vsim with a setting for the property vsimdir. Running "help vsim" in MATLAB will give you the i...

12년 초과 전 | 0

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Viterbi Decoder vitdec for HDL-Code generation
The Viterbi decoder expects to receive the systematic and parity bits in a vector format. Please change your input to a vector f...

12년 초과 전 | 0

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Viterbi Decoder vitdec for HDL-Code generation
There is also an example in the Communications System Toolbox (category HDL) called "HDL Code Generation for Viterbi Decoder" th...

12년 초과 전 | 0