HDL Verifier SystemVerilog DPI component generation with Synopsys VCS
This example was used in the video demonstration:
https://www.mathworks.com/videos/generate-systemverilog-dpi-components-for-simulation-with-synopsys-vcs-1495725854304.html
It illustrates how to re-use MATLAB functions and stimulus to more quickly build a Universal Verification Methodology testbench. Specifically it generates SystemVerilog DPI components from a MATLAB algorithm for use in a UVM scoreboard, and for a realistic video input for use as a UVM sequence item. The simulation is set up to run Synopsys VCS.
인용 양식
MathWorks HDLVerifier Team (2024). HDL Verifier SystemVerilog DPI component generation with Synopsys VCS (https://www.mathworks.com/matlabcentral/fileexchange/63335-hdl-verifier-systemverilog-dpi-component-generation-with-synopsys-vcs), MATLAB Central File Exchange. 검색됨 .
MATLAB 릴리스 호환 정보
플랫폼 호환성
Windows macOS Linux카테고리
- FPGA, ASIC, and SoC Development >
- Code Generation > HDL Verifier > ASIC Testbench > DPI Generation for Simulink Subsystem >
- FPGA, ASIC, and SoC Development > HDL Verifier > ASIC Testbench > DPI Generation for Simulink Subsystem >
태그
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!DPI_UVM_MATLAB_EnhancedEdgeDetect/
DPI_UVM_MATLAB_EnhancedEdgeDetect/DUT_HDL/
DPI_UVM_MATLAB_EnhancedEdgeDetect/codegen/dll/EED_scbd/html/resources/
DPI_UVM_MATLAB_EnhancedEdgeDetect/codegen/dll/Stimulus/html/resources/
버전 | 게시됨 | 릴리스 정보 | |
---|---|---|---|
1.0.0.0 |