Problem 326. Tricky timing

Solution 44741

Submitted on 18 Feb 2012 by Rick Rosson

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Test	Status	Code Input and Output
1	Pass	%% tic; y=foo(1); t2=toc assert((t2>.5)&&(t2<.6)) t2 = 0.575571000000000

Test

Status

Code Input and Output

Pass

%% tic; y=foo(1); t2=toc assert((t2>.5)&&(t2<.6))

t2 = 0.575571000000000

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