---------- Begin Simulation Statistics ---------- sim_seconds 0.010000 # Number of seconds simulated sim_ticks 10000000000 # Number of ticks simulated final_tick 20000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 2755573 # Simulator instruction rate (inst/s) host_op_rate 2755568 # Simulator op (including micro ops) rate (op/s) host_tick_rate 1950987782 # Simulator tick rate (ticks/s) host_mem_usage 1511996 # Number of bytes of host memory used host_seconds 5.13 # Real time elapsed on the host sim_insts 14123937 # Number of instructions simulated sim_ops 14123937 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::cpu00.inst 128 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu00.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu01.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu02.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu03.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu04.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu05.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu06.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu07.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu08.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu09.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu10.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu11.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu12.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu13.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu14.data 64 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu15.inst 128 # Number of bytes read from this memory system.mem_ctrls.bytes_read::cpu15.data 128 # Number of bytes read from this memory system.mem_ctrls.bytes_read::switch_cpus00.inst 57920 # Number of bytes read from this memory system.mem_ctrls.bytes_read::switch_cpus00.data 9411456 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 9470720 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::cpu00.inst 128 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::cpu15.inst 128 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::switch_cpus00.inst 57920 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 58176 # Number of instructions bytes read from this memory system.mem_ctrls.num_reads::cpu00.inst 2 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu00.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu01.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu02.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu03.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu04.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu05.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu06.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu07.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu08.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu09.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu10.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu11.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu12.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu13.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu14.data 1 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu15.inst 2 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::cpu15.data 2 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::switch_cpus00.inst 905 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::switch_cpus00.data 147054 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 147980 # Number of read requests responded to by this memory system.mem_ctrls.bw_read::cpu00.inst 12800 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu00.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu01.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu02.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu03.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu04.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu05.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu06.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu07.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu08.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu09.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu10.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu11.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu12.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu13.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu14.data 6400 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu15.inst 12800 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::cpu15.data 12800 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::switch_cpus00.inst 5792000 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::switch_cpus00.data 941145600 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 947072000 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::cpu00.inst 12800 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::cpu15.inst 12800 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::switch_cpus00.inst 5792000 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 5817600 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::cpu00.inst 12800 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu00.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu01.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu02.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu03.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu04.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu05.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu06.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu07.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu08.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu09.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu10.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu11.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu12.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu13.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu14.data 6400 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu15.inst 12800 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::cpu15.data 12800 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::switch_cpus00.inst 5792000 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::switch_cpus00.data 941145600 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 947072000 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 21 # Number of read requests accepted system.mem_ctrls.writeReqs 0 # Number of write requests accepted system.mem_ctrls.readBursts 21 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.bytesReadDRAM 1344 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 1344 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 4 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.totGap 20744000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 21 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 5 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 6 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 224 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 151.506786 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 245.379706 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::64-127 2 33.33% 33.33% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-191 2 33.33% 66.67% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-319 1 16.67% 83.33% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::704-767 1 16.67% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 6 # Bytes accessed per row activation system.mem_ctrls.totQLat 872235 # Total ticks spent queuing system.mem_ctrls.totMemAccLat 1265985 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 105000 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 41535.00 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 60285.00 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 0.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 0.13 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.00 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.00 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 15.97 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 15 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 71.43 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes system.mem_ctrls.avgGap 987809.52 # Average gap between requests system.mem_ctrls.pageHitRate 71.43 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 7140 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 3795 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 14280 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 372210 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 3836728800 # Energy for precharge background per rank (pJ) system.mem_ctrls_0.actPowerDownEnergy 3512340 # Energy for active power-down per rank (pJ) system.mem_ctrls_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls_0.totalEnergy 3842482485 # Total energy per rank (pJ) system.mem_ctrls_0.averagePower 384.248248 # Core power per rank (mW) system.mem_ctrls_0.totalIdleTime 7701500 # Total Idle time Per DRAM Rank system.mem_ctrls_0.memoryStateTime::IDLE 9991426000 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 780000 # Time in different power states system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT 92500 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 7701500 # Time in different power states system.mem_ctrls_1.actEnergy 35700 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 18975 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 135660 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls_1.actBackEnergy 434910 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 3835697280 # Energy for precharge background per rank (pJ) system.mem_ctrls_1.actPowerDownEnergy 4674570 # Energy for active power-down per rank (pJ) system.mem_ctrls_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls_1.totalEnergy 3842841015 # Total energy per rank (pJ) system.mem_ctrls_1.averagePower 384.284102 # Core power per rank (mW) system.mem_ctrls_1.totalIdleTime 10250250 # Total Idle time Per DRAM Rank system.mem_ctrls_1.memoryStateTime::IDLE 9988726000 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 780000 # Time in different power states system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 243750 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 10250250 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.bridge.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.branchPred.lookups 2 # Number of BP lookups system.cpu00.branchPred.condPredicted 1 # Number of conditional branches predicted system.cpu00.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu00.branchPred.BTBLookups 0 # Number of BTB lookups system.cpu00.branchPred.BTBHits 0 # Number of BTB hits system.cpu00.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu00.branchPred.BTBHitPct nan # BTB Hit Percentage system.cpu00.branchPred.usedRAS 1 # Number of times the RAS was used to get a target. system.cpu00.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. system.cpu00.branchPred.indirectLookups 0 # Number of indirect predictor lookups. system.cpu00.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu00.branchPred.indirectMisses 0 # Number of indirect misses. system.cpu00.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu00.dtb.fetch_hits 0 # ITB hits system.cpu00.dtb.fetch_misses 0 # ITB misses system.cpu00.dtb.fetch_acv 0 # ITB acv system.cpu00.dtb.fetch_accesses 0 # ITB accesses system.cpu00.dtb.read_hits 1 # DTB read hits system.cpu00.dtb.read_misses 0 # DTB read misses system.cpu00.dtb.read_acv 0 # DTB read access violations system.cpu00.dtb.read_accesses 0 # DTB read accesses system.cpu00.dtb.write_hits 0 # DTB write hits system.cpu00.dtb.write_misses 0 # DTB write misses system.cpu00.dtb.write_acv 0 # DTB write access violations system.cpu00.dtb.write_accesses 0 # DTB write accesses system.cpu00.dtb.data_hits 1 # DTB hits system.cpu00.dtb.data_misses 0 # DTB misses system.cpu00.dtb.data_acv 0 # DTB access violations system.cpu00.dtb.data_accesses 0 # DTB accesses system.cpu00.itb.fetch_hits 0 # ITB hits system.cpu00.itb.fetch_misses 1 # ITB misses system.cpu00.itb.fetch_acv 0 # ITB acv system.cpu00.itb.fetch_accesses 1 # ITB accesses system.cpu00.itb.read_hits 0 # DTB read hits system.cpu00.itb.read_misses 0 # DTB read misses system.cpu00.itb.read_acv 0 # DTB read access violations system.cpu00.itb.read_accesses 0 # DTB read accesses system.cpu00.itb.write_hits 0 # DTB write hits system.cpu00.itb.write_misses 0 # DTB write misses system.cpu00.itb.write_acv 0 # DTB write access violations system.cpu00.itb.write_accesses 0 # DTB write accesses system.cpu00.itb.data_hits 0 # DTB hits system.cpu00.itb.data_misses 0 # DTB misses system.cpu00.itb.data_acv 0 # DTB access violations system.cpu00.itb.data_accesses 0 # DTB accesses system.cpu00.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu00.numCycles 360 # number of cpu cycles simulated system.cpu00.numWorkItemsStarted 0 # number of work items this cpu started system.cpu00.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu00.fetch.icacheStallCycles 35 # Number of cycles fetch is stalled on an Icache miss system.cpu00.fetch.Insts 7 # Number of instructions fetch has processed system.cpu00.fetch.Branches 2 # Number of branches that fetch encountered system.cpu00.fetch.predictedBranches 1 # Number of branches that fetch has predicted taken system.cpu00.fetch.Cycles 1 # Number of cycles fetch has run and was not squashing or blocked system.cpu00.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu00.fetch.PendingDrainCycles 3 # Number of cycles fetch has spent waiting on pipes to drain system.cpu00.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps system.cpu00.fetch.CacheLines 2 # Number of cache lines fetched system.cpu00.fetch.IcacheSquashes 1 # Number of outstanding Icache misses that were squashed system.cpu00.fetch.rateDist::samples 46 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::mean 0.152174 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::stdev 1.032094 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::0 45 97.83% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::1 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::2 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::3 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::4 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::5 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::6 0 0.00% 97.83% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::7 1 2.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::max_value 7 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.rateDist::total 46 # Number of instructions fetched each cycle (Total) system.cpu00.fetch.branchRate 0.005556 # Number of branch fetches per cycle system.cpu00.fetch.rate 0.019444 # Number of inst fetches per cycle system.cpu00.decode.IdleCycles 43 # Number of cycles decode is idle system.cpu00.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu00.decode.DecodedInsts 8 # Number of instructions handled by decode system.cpu00.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu00.rename.IdleCycles 43 # Number of cycles rename is idle system.cpu00.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu00.rename.RunCycles 0 # Number of cycles rename is running system.cpu00.rename.RenamedInsts 8 # Number of instructions processed by rename system.cpu00.rename.RenamedOperands 5 # Number of destination operands rename has renamed system.cpu00.rename.RenameLookups 10 # Number of register rename lookups that rename has made system.cpu00.rename.int_rename_lookups 10 # Number of integer rename lookups system.cpu00.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu00.rename.UndoneMaps 4 # Number of HB maps that are undone due to squashing system.cpu00.rename.serializingInsts 0 # count of serializing insts renamed system.cpu00.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu00.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu00.memDep0.insertedLoads 1 # Number of loads inserted to the mem dependence unit. system.cpu00.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu00.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu00.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu00.iq.iqInstsAdded 7 # Number of instructions added to the IQ (excludes non-spec) system.cpu00.iq.iqInstsIssued 6 # Number of instructions issued system.cpu00.iq.iqSquashedInstsExamined 6 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu00.iq.iqSquashedOperandsExamined 1 # Number of squashed operands that are examined and possibly removed from graph system.cpu00.iq.issued_per_cycle::samples 46 # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::mean 0.130435 # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::stdev 0.499275 # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::0 42 91.30% 91.30% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::1 3 6.52% 97.83% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::2 0 0.00% 97.83% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::3 1 2.17% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu00.iq.issued_per_cycle::total 46 # Number of insts issued each cycle system.cpu00.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu00.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu00.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu00.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu00.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu00.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu00.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu00.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu00.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu00.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu00.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu00.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu00.iq.FU_type_0::IntMult 1 16.67% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::IntDiv 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatAdd 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatCmp 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatCvt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatMult 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatMultAcc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatDiv 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatMisc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::FloatSqrt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdAdd 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdAddAcc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdAlu 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdCmp 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdCvt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdMisc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdMult 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdMultAcc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdShift 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdShiftAcc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdSqrt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatAdd 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatAlu 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatCmp 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatCvt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatDiv 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatMisc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatMult 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::SimdFloatSqrt 0 0.00% 83.33% # Type of FU issued system.cpu00.iq.FU_type_0::MemRead 1 16.67% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu00.iq.FU_type_0::total 6 # Type of FU issued system.cpu00.iq.rate 0.016667 # Inst issue rate system.cpu00.iq.fu_busy_cnt 0 # FU busy when requested system.cpu00.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu00.iq.int_inst_queue_reads 58 # Number of integer instruction queue reads system.cpu00.iq.int_inst_queue_writes 13 # Number of integer instruction queue writes system.cpu00.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu00.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu00.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu00.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu00.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu00.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu00.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu00.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu00.iew.lsq.thread0.squashedLoads 0 # Number of loads squashed system.cpu00.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu00.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu00.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu00.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu00.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu00.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu00.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu00.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu00.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu00.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu00.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu00.iew.iewDispatchedInsts 8 # Number of instructions dispatched to IQ system.cpu00.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu00.iew.iewDispLoadInsts 1 # Number of dispatched load instructions system.cpu00.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu00.iew.iewDispNonSpecInsts 0 # Number of dispatched non-speculative instructions system.cpu00.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu00.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu00.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu00.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly system.cpu00.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly system.cpu00.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu00.iew.iewExecutedInsts 5 # Number of executed instructions system.cpu00.iew.iewExecLoadInsts 1 # Number of load instructions executed system.cpu00.iew.iewExecSquashedInsts 1 # Number of squashed instructions skipped in execute system.cpu00.iew.exec_swp 0 # number of swp insts executed system.cpu00.iew.exec_nop 1 # number of nop insts executed system.cpu00.iew.exec_refs 1 # number of memory reference insts executed system.cpu00.iew.exec_branches 1 # Number of branches executed system.cpu00.iew.exec_stores 0 # Number of stores executed system.cpu00.iew.exec_rate 0.013889 # Inst execution rate system.cpu00.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu00.iew.wb_count 5 # cumulative count of insts written-back system.cpu00.iew.wb_producers 4 # num instructions producing a value system.cpu00.iew.wb_consumers 4 # num instructions consuming a value system.cpu00.iew.wb_rate 0.013889 # insts written-back per cycle system.cpu00.iew.wb_fanout 1 # average fanout of values written-back system.cpu00.commit.commitSquashedInsts 7 # The number of squashed insts skipped by commit system.cpu00.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu00.commit.committed_per_cycle::samples 44 # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::mean 0.022727 # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::stdev 0.150756 # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::0 43 97.73% 97.73% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::1 1 2.27% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu00.commit.committed_per_cycle::total 44 # Number of insts commited each cycle system.cpu00.commit.committedInsts 1 # Number of instructions committed system.cpu00.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu00.commit.swp_count 0 # Number of s/w prefetches committed system.cpu00.commit.refs 1 # Number of memory references committed system.cpu00.commit.loads 1 # Number of loads committed system.cpu00.commit.membars 0 # Number of memory barriers committed system.cpu00.commit.branches 0 # Number of branches committed system.cpu00.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu00.commit.int_insts 1 # Number of committed integer instructions. system.cpu00.commit.function_calls 0 # Number of function calls committed. system.cpu00.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu00.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu00.commit.op_class_0::total 1 # Class of committed instruction system.cpu00.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu00.rob.rob_reads 51 # The number of ROB reads system.cpu00.rob.rob_writes 18 # The number of ROB writes system.cpu00.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu00.idleCycles 314 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu00.committedInsts 1 # Number of Instructions Simulated system.cpu00.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu00.cpi 360.000000 # CPI: Cycles Per Instruction system.cpu00.cpi_total 360.000000 # CPI: Total CPI of All Threads system.cpu00.ipc 0.002778 # IPC: Instructions Per Cycle system.cpu00.ipc_total 0.002778 # IPC: Total IPC of All Threads system.cpu00.int_regfile_reads 47 # number of integer regfile reads system.cpu00.int_regfile_writes 4 # number of integer regfile writes system.cpu00.fp_regfile_reads 32 # number of floating regfile reads system.cpu00.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.dcache.tags.replacements 255574 # number of replacements system.cpu00.dcache.tags.tagsinuse 510.353838 # Cycle average of tags in use system.cpu00.dcache.tags.total_refs 3026919 # Total number of references to valid blocks. system.cpu00.dcache.tags.sampled_refs 256086 # Sample count of references to valid blocks. system.cpu00.dcache.tags.avg_refs 11.819932 # Average number of references to valid blocks. system.cpu00.dcache.tags.warmup_cycle 10041185500 # Cycle when the warmup percentage was hit. system.cpu00.dcache.tags.occ_blocks::cpu00.data 0.065730 # Average occupied blocks per requestor system.cpu00.dcache.tags.occ_blocks::switch_cpus00.data 510.288108 # Average occupied blocks per requestor system.cpu00.dcache.tags.occ_percent::cpu00.data 0.000128 # Average percentage of cache occupancy system.cpu00.dcache.tags.occ_percent::switch_cpus00.data 0.996656 # Average percentage of cache occupancy system.cpu00.dcache.tags.occ_percent::total 0.996785 # Average percentage of cache occupancy system.cpu00.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu00.dcache.tags.age_task_id_blocks_1024::0 350 # Occupied blocks per task id system.cpu00.dcache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id system.cpu00.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu00.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu00.dcache.tags.tag_accesses 13388106 # Number of tag accesses system.cpu00.dcache.tags.data_accesses 13388106 # Number of data accesses system.cpu00.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.dcache.ReadReq_hits::switch_cpus00.data 2120865 # number of ReadReq hits system.cpu00.dcache.ReadReq_hits::total 2120865 # number of ReadReq hits system.cpu00.dcache.WriteReq_hits::switch_cpus00.data 842878 # number of WriteReq hits system.cpu00.dcache.WriteReq_hits::total 842878 # number of WriteReq hits system.cpu00.dcache.LoadLockedReq_hits::switch_cpus00.data 31573 # number of LoadLockedReq hits system.cpu00.dcache.LoadLockedReq_hits::total 31573 # number of LoadLockedReq hits system.cpu00.dcache.StoreCondReq_hits::switch_cpus00.data 31603 # number of StoreCondReq hits system.cpu00.dcache.StoreCondReq_hits::total 31603 # number of StoreCondReq hits system.cpu00.dcache.demand_hits::switch_cpus00.data 2963743 # number of demand (read+write) hits system.cpu00.dcache.demand_hits::total 2963743 # number of demand (read+write) hits system.cpu00.dcache.overall_hits::switch_cpus00.data 2963743 # number of overall hits system.cpu00.dcache.overall_hits::total 2963743 # number of overall hits system.cpu00.dcache.ReadReq_misses::cpu00.data 1 # number of ReadReq misses system.cpu00.dcache.ReadReq_misses::switch_cpus00.data 164318 # number of ReadReq misses system.cpu00.dcache.ReadReq_misses::total 164319 # number of ReadReq misses system.cpu00.dcache.WriteReq_misses::switch_cpus00.data 91737 # number of WriteReq misses system.cpu00.dcache.WriteReq_misses::total 91737 # number of WriteReq misses system.cpu00.dcache.LoadLockedReq_misses::switch_cpus00.data 30 # number of LoadLockedReq misses system.cpu00.dcache.LoadLockedReq_misses::total 30 # number of LoadLockedReq misses system.cpu00.dcache.demand_misses::cpu00.data 1 # number of demand (read+write) misses system.cpu00.dcache.demand_misses::switch_cpus00.data 256055 # number of demand (read+write) misses system.cpu00.dcache.demand_misses::total 256056 # number of demand (read+write) misses system.cpu00.dcache.overall_misses::cpu00.data 1 # number of overall misses system.cpu00.dcache.overall_misses::switch_cpus00.data 256055 # number of overall misses system.cpu00.dcache.overall_misses::total 256056 # number of overall misses system.cpu00.dcache.ReadReq_miss_latency::cpu00.data 86500 # number of ReadReq miss cycles system.cpu00.dcache.ReadReq_miss_latency::total 86500 # number of ReadReq miss cycles system.cpu00.dcache.demand_miss_latency::cpu00.data 86500 # number of demand (read+write) miss cycles system.cpu00.dcache.demand_miss_latency::total 86500 # number of demand (read+write) miss cycles system.cpu00.dcache.overall_miss_latency::cpu00.data 86500 # number of overall miss cycles system.cpu00.dcache.overall_miss_latency::total 86500 # number of overall miss cycles system.cpu00.dcache.ReadReq_accesses::cpu00.data 1 # number of ReadReq accesses(hits+misses) system.cpu00.dcache.ReadReq_accesses::switch_cpus00.data 2285183 # number of ReadReq accesses(hits+misses) system.cpu00.dcache.ReadReq_accesses::total 2285184 # number of ReadReq accesses(hits+misses) system.cpu00.dcache.WriteReq_accesses::switch_cpus00.data 934615 # number of WriteReq accesses(hits+misses) system.cpu00.dcache.WriteReq_accesses::total 934615 # number of WriteReq accesses(hits+misses) system.cpu00.dcache.LoadLockedReq_accesses::switch_cpus00.data 31603 # number of LoadLockedReq accesses(hits+misses) system.cpu00.dcache.LoadLockedReq_accesses::total 31603 # number of LoadLockedReq accesses(hits+misses) system.cpu00.dcache.StoreCondReq_accesses::switch_cpus00.data 31603 # number of StoreCondReq accesses(hits+misses) system.cpu00.dcache.StoreCondReq_accesses::total 31603 # number of StoreCondReq accesses(hits+misses) system.cpu00.dcache.demand_accesses::cpu00.data 1 # number of demand (read+write) accesses system.cpu00.dcache.demand_accesses::switch_cpus00.data 3219798 # number of demand (read+write) accesses system.cpu00.dcache.demand_accesses::total 3219799 # number of demand (read+write) accesses system.cpu00.dcache.overall_accesses::cpu00.data 1 # number of overall (read+write) accesses system.cpu00.dcache.overall_accesses::switch_cpus00.data 3219798 # number of overall (read+write) accesses system.cpu00.dcache.overall_accesses::total 3219799 # number of overall (read+write) accesses system.cpu00.dcache.ReadReq_miss_rate::cpu00.data 1 # miss rate for ReadReq accesses system.cpu00.dcache.ReadReq_miss_rate::switch_cpus00.data 0.071906 # miss rate for ReadReq accesses system.cpu00.dcache.ReadReq_miss_rate::total 0.071906 # miss rate for ReadReq accesses system.cpu00.dcache.WriteReq_miss_rate::switch_cpus00.data 0.098155 # miss rate for WriteReq accesses system.cpu00.dcache.WriteReq_miss_rate::total 0.098155 # miss rate for WriteReq accesses system.cpu00.dcache.LoadLockedReq_miss_rate::switch_cpus00.data 0.000949 # miss rate for LoadLockedReq accesses system.cpu00.dcache.LoadLockedReq_miss_rate::total 0.000949 # miss rate for LoadLockedReq accesses system.cpu00.dcache.demand_miss_rate::cpu00.data 1 # miss rate for demand accesses system.cpu00.dcache.demand_miss_rate::switch_cpus00.data 0.079525 # miss rate for demand accesses system.cpu00.dcache.demand_miss_rate::total 0.079525 # miss rate for demand accesses system.cpu00.dcache.overall_miss_rate::cpu00.data 1 # miss rate for overall accesses system.cpu00.dcache.overall_miss_rate::switch_cpus00.data 0.079525 # miss rate for overall accesses system.cpu00.dcache.overall_miss_rate::total 0.079525 # miss rate for overall accesses system.cpu00.dcache.ReadReq_avg_miss_latency::cpu00.data 86500 # average ReadReq miss latency system.cpu00.dcache.ReadReq_avg_miss_latency::total 0.526415 # average ReadReq miss latency system.cpu00.dcache.demand_avg_miss_latency::cpu00.data 86500 # average overall miss latency system.cpu00.dcache.demand_avg_miss_latency::total 0.337817 # average overall miss latency system.cpu00.dcache.overall_avg_miss_latency::cpu00.data 86500 # average overall miss latency system.cpu00.dcache.overall_avg_miss_latency::total 0.337817 # average overall miss latency system.cpu00.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu00.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu00.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu00.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu00.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu00.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu00.dcache.writebacks::writebacks 252639 # number of writebacks system.cpu00.dcache.writebacks::total 252639 # number of writebacks system.cpu00.dcache.ReadReq_mshr_misses::cpu00.data 1 # number of ReadReq MSHR misses system.cpu00.dcache.ReadReq_mshr_misses::total 1 # number of ReadReq MSHR misses system.cpu00.dcache.demand_mshr_misses::cpu00.data 1 # number of demand (read+write) MSHR misses system.cpu00.dcache.demand_mshr_misses::total 1 # number of demand (read+write) MSHR misses system.cpu00.dcache.overall_mshr_misses::cpu00.data 1 # number of overall MSHR misses system.cpu00.dcache.overall_mshr_misses::total 1 # number of overall MSHR misses system.cpu00.dcache.ReadReq_mshr_miss_latency::cpu00.data 85500 # number of ReadReq MSHR miss cycles system.cpu00.dcache.ReadReq_mshr_miss_latency::total 85500 # number of ReadReq MSHR miss cycles system.cpu00.dcache.demand_mshr_miss_latency::cpu00.data 85500 # number of demand (read+write) MSHR miss cycles system.cpu00.dcache.demand_mshr_miss_latency::total 85500 # number of demand (read+write) MSHR miss cycles system.cpu00.dcache.overall_mshr_miss_latency::cpu00.data 85500 # number of overall MSHR miss cycles system.cpu00.dcache.overall_mshr_miss_latency::total 85500 # number of overall MSHR miss cycles system.cpu00.dcache.ReadReq_mshr_miss_rate::cpu00.data 1 # mshr miss rate for ReadReq accesses system.cpu00.dcache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu00.dcache.demand_mshr_miss_rate::cpu00.data 1 # mshr miss rate for demand accesses system.cpu00.dcache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu00.dcache.overall_mshr_miss_rate::cpu00.data 1 # mshr miss rate for overall accesses system.cpu00.dcache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu00.dcache.ReadReq_avg_mshr_miss_latency::cpu00.data 85500 # average ReadReq mshr miss latency system.cpu00.dcache.ReadReq_avg_mshr_miss_latency::total 85500 # average ReadReq mshr miss latency system.cpu00.dcache.demand_avg_mshr_miss_latency::cpu00.data 85500 # average overall mshr miss latency system.cpu00.dcache.demand_avg_mshr_miss_latency::total 85500 # average overall mshr miss latency system.cpu00.dcache.overall_avg_mshr_miss_latency::cpu00.data 85500 # average overall mshr miss latency system.cpu00.dcache.overall_avg_mshr_miss_latency::total 85500 # average overall mshr miss latency system.cpu00.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.icache.tags.replacements 578 # number of replacements system.cpu00.icache.tags.tagsinuse 436.434333 # Cycle average of tags in use system.cpu00.icache.tags.total_refs 14120564 # Total number of references to valid blocks. system.cpu00.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. system.cpu00.icache.tags.avg_refs 13086.713624 # Average number of references to valid blocks. system.cpu00.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu00.icache.tags.occ_blocks::cpu00.inst 0.166684 # Average occupied blocks per requestor system.cpu00.icache.tags.occ_blocks::switch_cpus00.inst 436.267649 # Average occupied blocks per requestor system.cpu00.icache.tags.occ_percent::cpu00.inst 0.000326 # Average percentage of cache occupancy system.cpu00.icache.tags.occ_percent::switch_cpus00.inst 0.852085 # Average percentage of cache occupancy system.cpu00.icache.tags.occ_percent::total 0.852411 # Average percentage of cache occupancy system.cpu00.icache.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id system.cpu00.icache.tags.age_task_id_blocks_1024::3 501 # Occupied blocks per task id system.cpu00.icache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id system.cpu00.icache.tags.tag_accesses 56487651 # Number of tag accesses system.cpu00.icache.tags.data_accesses 56487651 # Number of data accesses system.cpu00.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.icache.ReadReq_hits::switch_cpus00.inst 14120564 # number of ReadReq hits system.cpu00.icache.ReadReq_hits::total 14120564 # number of ReadReq hits system.cpu00.icache.demand_hits::switch_cpus00.inst 14120564 # number of demand (read+write) hits system.cpu00.icache.demand_hits::total 14120564 # number of demand (read+write) hits system.cpu00.icache.overall_hits::switch_cpus00.inst 14120564 # number of overall hits system.cpu00.icache.overall_hits::total 14120564 # number of overall hits system.cpu00.icache.ReadReq_misses::cpu00.inst 2 # number of ReadReq misses system.cpu00.icache.ReadReq_misses::switch_cpus00.inst 1077 # number of ReadReq misses system.cpu00.icache.ReadReq_misses::total 1079 # number of ReadReq misses system.cpu00.icache.demand_misses::cpu00.inst 2 # number of demand (read+write) misses system.cpu00.icache.demand_misses::switch_cpus00.inst 1077 # number of demand (read+write) misses system.cpu00.icache.demand_misses::total 1079 # number of demand (read+write) misses system.cpu00.icache.overall_misses::cpu00.inst 2 # number of overall misses system.cpu00.icache.overall_misses::switch_cpus00.inst 1077 # number of overall misses system.cpu00.icache.overall_misses::total 1079 # number of overall misses system.cpu00.icache.ReadReq_miss_latency::cpu00.inst 180000 # number of ReadReq miss cycles system.cpu00.icache.ReadReq_miss_latency::total 180000 # number of ReadReq miss cycles system.cpu00.icache.demand_miss_latency::cpu00.inst 180000 # number of demand (read+write) miss cycles system.cpu00.icache.demand_miss_latency::total 180000 # number of demand (read+write) miss cycles system.cpu00.icache.overall_miss_latency::cpu00.inst 180000 # number of overall miss cycles system.cpu00.icache.overall_miss_latency::total 180000 # number of overall miss cycles system.cpu00.icache.ReadReq_accesses::cpu00.inst 2 # number of ReadReq accesses(hits+misses) system.cpu00.icache.ReadReq_accesses::switch_cpus00.inst 14121641 # number of ReadReq accesses(hits+misses) system.cpu00.icache.ReadReq_accesses::total 14121643 # number of ReadReq accesses(hits+misses) system.cpu00.icache.demand_accesses::cpu00.inst 2 # number of demand (read+write) accesses system.cpu00.icache.demand_accesses::switch_cpus00.inst 14121641 # number of demand (read+write) accesses system.cpu00.icache.demand_accesses::total 14121643 # number of demand (read+write) accesses system.cpu00.icache.overall_accesses::cpu00.inst 2 # number of overall (read+write) accesses system.cpu00.icache.overall_accesses::switch_cpus00.inst 14121641 # number of overall (read+write) accesses system.cpu00.icache.overall_accesses::total 14121643 # number of overall (read+write) accesses system.cpu00.icache.ReadReq_miss_rate::cpu00.inst 1 # miss rate for ReadReq accesses system.cpu00.icache.ReadReq_miss_rate::switch_cpus00.inst 0.000076 # miss rate for ReadReq accesses system.cpu00.icache.ReadReq_miss_rate::total 0.000076 # miss rate for ReadReq accesses system.cpu00.icache.demand_miss_rate::cpu00.inst 1 # miss rate for demand accesses system.cpu00.icache.demand_miss_rate::switch_cpus00.inst 0.000076 # miss rate for demand accesses system.cpu00.icache.demand_miss_rate::total 0.000076 # miss rate for demand accesses system.cpu00.icache.overall_miss_rate::cpu00.inst 1 # miss rate for overall accesses system.cpu00.icache.overall_miss_rate::switch_cpus00.inst 0.000076 # miss rate for overall accesses system.cpu00.icache.overall_miss_rate::total 0.000076 # miss rate for overall accesses system.cpu00.icache.ReadReq_avg_miss_latency::cpu00.inst 90000 # average ReadReq miss latency system.cpu00.icache.ReadReq_avg_miss_latency::total 166.821131 # average ReadReq miss latency system.cpu00.icache.demand_avg_miss_latency::cpu00.inst 90000 # average overall miss latency system.cpu00.icache.demand_avg_miss_latency::total 166.821131 # average overall miss latency system.cpu00.icache.overall_avg_miss_latency::cpu00.inst 90000 # average overall miss latency system.cpu00.icache.overall_avg_miss_latency::total 166.821131 # average overall miss latency system.cpu00.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu00.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu00.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu00.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu00.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu00.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu00.icache.writebacks::writebacks 578 # number of writebacks system.cpu00.icache.writebacks::total 578 # number of writebacks system.cpu00.icache.ReadReq_mshr_misses::cpu00.inst 2 # number of ReadReq MSHR misses system.cpu00.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu00.icache.demand_mshr_misses::cpu00.inst 2 # number of demand (read+write) MSHR misses system.cpu00.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu00.icache.overall_mshr_misses::cpu00.inst 2 # number of overall MSHR misses system.cpu00.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu00.icache.ReadReq_mshr_miss_latency::cpu00.inst 178000 # number of ReadReq MSHR miss cycles system.cpu00.icache.ReadReq_mshr_miss_latency::total 178000 # number of ReadReq MSHR miss cycles system.cpu00.icache.demand_mshr_miss_latency::cpu00.inst 178000 # number of demand (read+write) MSHR miss cycles system.cpu00.icache.demand_mshr_miss_latency::total 178000 # number of demand (read+write) MSHR miss cycles system.cpu00.icache.overall_mshr_miss_latency::cpu00.inst 178000 # number of overall MSHR miss cycles system.cpu00.icache.overall_mshr_miss_latency::total 178000 # number of overall MSHR miss cycles system.cpu00.icache.ReadReq_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for ReadReq accesses system.cpu00.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu00.icache.demand_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for demand accesses system.cpu00.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu00.icache.overall_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for overall accesses system.cpu00.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu00.icache.ReadReq_avg_mshr_miss_latency::cpu00.inst 89000 # average ReadReq mshr miss latency system.cpu00.icache.ReadReq_avg_mshr_miss_latency::total 89000 # average ReadReq mshr miss latency system.cpu00.icache.demand_avg_mshr_miss_latency::cpu00.inst 89000 # average overall mshr miss latency system.cpu00.icache.demand_avg_mshr_miss_latency::total 89000 # average overall mshr miss latency system.cpu00.icache.overall_avg_mshr_miss_latency::cpu00.inst 89000 # average overall mshr miss latency system.cpu00.icache.overall_avg_mshr_miss_latency::total 89000 # average overall mshr miss latency system.cpu01.branchPred.lookups 5 # Number of BP lookups system.cpu01.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu01.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu01.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu01.branchPred.BTBHits 0 # Number of BTB hits system.cpu01.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu01.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu01.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu01.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu01.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu01.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu01.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu01.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu01.dtb.fetch_hits 0 # ITB hits system.cpu01.dtb.fetch_misses 0 # ITB misses system.cpu01.dtb.fetch_acv 0 # ITB acv system.cpu01.dtb.fetch_accesses 0 # ITB accesses system.cpu01.dtb.read_hits 2 # DTB read hits system.cpu01.dtb.read_misses 0 # DTB read misses system.cpu01.dtb.read_acv 0 # DTB read access violations system.cpu01.dtb.read_accesses 0 # DTB read accesses system.cpu01.dtb.write_hits 0 # DTB write hits system.cpu01.dtb.write_misses 0 # DTB write misses system.cpu01.dtb.write_acv 0 # DTB write access violations system.cpu01.dtb.write_accesses 0 # DTB write accesses system.cpu01.dtb.data_hits 2 # DTB hits system.cpu01.dtb.data_misses 0 # DTB misses system.cpu01.dtb.data_acv 0 # DTB access violations system.cpu01.dtb.data_accesses 0 # DTB accesses system.cpu01.itb.fetch_hits 0 # ITB hits system.cpu01.itb.fetch_misses 1 # ITB misses system.cpu01.itb.fetch_acv 0 # ITB acv system.cpu01.itb.fetch_accesses 1 # ITB accesses system.cpu01.itb.read_hits 0 # DTB read hits system.cpu01.itb.read_misses 0 # DTB read misses system.cpu01.itb.read_acv 0 # DTB read access violations system.cpu01.itb.read_accesses 0 # DTB read accesses system.cpu01.itb.write_hits 0 # DTB write hits system.cpu01.itb.write_misses 0 # DTB write misses system.cpu01.itb.write_acv 0 # DTB write access violations system.cpu01.itb.write_accesses 0 # DTB write accesses system.cpu01.itb.data_hits 0 # DTB hits system.cpu01.itb.data_misses 0 # DTB misses system.cpu01.itb.data_acv 0 # DTB access violations system.cpu01.itb.data_accesses 0 # DTB accesses system.cpu01.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu01.numCycles 641 # number of cpu cycles simulated system.cpu01.numWorkItemsStarted 0 # number of work items this cpu started system.cpu01.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu01.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu01.fetch.Insts 10 # Number of instructions fetch has processed system.cpu01.fetch.Branches 5 # Number of branches that fetch encountered system.cpu01.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu01.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu01.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu01.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu01.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu01.fetch.CacheLines 3 # Number of cache lines fetched system.cpu01.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu01.fetch.branchRate 0.007800 # Number of branch fetches per cycle system.cpu01.fetch.rate 0.015601 # Number of inst fetches per cycle system.cpu01.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu01.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu01.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu01.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu01.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu01.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu01.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu01.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu01.rename.RunCycles 0 # Number of cycles rename is running system.cpu01.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu01.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu01.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu01.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu01.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu01.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu01.rename.serializingInsts 0 # count of serializing insts renamed system.cpu01.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu01.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu01.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu01.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu01.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu01.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu01.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu01.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu01.iq.iqInstsIssued 6 # Number of instructions issued system.cpu01.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu01.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu01.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu01.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu01.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu01.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu01.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu01.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu01.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu01.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu01.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu01.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu01.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu01.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu01.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu01.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu01.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu01.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu01.iq.FU_type_0::total 6 # Type of FU issued system.cpu01.iq.rate 0.009360 # Inst issue rate system.cpu01.iq.fu_busy_cnt 0 # FU busy when requested system.cpu01.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu01.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu01.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu01.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu01.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu01.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu01.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu01.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu01.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu01.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu01.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu01.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu01.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu01.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu01.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu01.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu01.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu01.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu01.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu01.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu01.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu01.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu01.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu01.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu01.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu01.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu01.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu01.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu01.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu01.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu01.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu01.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu01.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu01.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu01.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu01.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu01.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu01.iew.exec_swp 0 # number of swp insts executed system.cpu01.iew.exec_nop 1 # number of nop insts executed system.cpu01.iew.exec_refs 2 # number of memory reference insts executed system.cpu01.iew.exec_branches 1 # Number of branches executed system.cpu01.iew.exec_stores 0 # Number of stores executed system.cpu01.iew.exec_rate 0.009360 # Inst execution rate system.cpu01.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu01.iew.wb_count 5 # cumulative count of insts written-back system.cpu01.iew.wb_producers 1 # num instructions producing a value system.cpu01.iew.wb_consumers 1 # num instructions consuming a value system.cpu01.iew.wb_rate 0.007800 # insts written-back per cycle system.cpu01.iew.wb_fanout 1 # average fanout of values written-back system.cpu01.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu01.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu01.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu01.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu01.commit.committedInsts 1 # Number of instructions committed system.cpu01.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu01.commit.swp_count 0 # Number of s/w prefetches committed system.cpu01.commit.refs 1 # Number of memory references committed system.cpu01.commit.loads 1 # Number of loads committed system.cpu01.commit.membars 0 # Number of memory barriers committed system.cpu01.commit.branches 0 # Number of branches committed system.cpu01.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu01.commit.int_insts 1 # Number of committed integer instructions. system.cpu01.commit.function_calls 0 # Number of function calls committed. system.cpu01.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu01.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu01.commit.op_class_0::total 1 # Class of committed instruction system.cpu01.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu01.rob.rob_reads 60 # The number of ROB reads system.cpu01.rob.rob_writes 26 # The number of ROB writes system.cpu01.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu01.idleCycles 587 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu01.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu01.committedInsts 1 # Number of Instructions Simulated system.cpu01.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu01.cpi 641.000000 # CPI: Cycles Per Instruction system.cpu01.cpi_total 641.000000 # CPI: Total CPI of All Threads system.cpu01.ipc 0.001560 # IPC: Instructions Per Cycle system.cpu01.ipc_total 0.001560 # IPC: Total IPC of All Threads system.cpu01.int_regfile_reads 48 # number of integer regfile reads system.cpu01.int_regfile_writes 4 # number of integer regfile writes system.cpu01.fp_regfile_reads 32 # number of floating regfile reads system.cpu01.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu01.dcache.tags.replacements 0 # number of replacements system.cpu01.dcache.tags.tagsinuse 1.995820 # Cycle average of tags in use system.cpu01.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu01.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu01.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu01.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu01.dcache.tags.occ_blocks::cpu01.data 1.995820 # Average occupied blocks per requestor system.cpu01.dcache.tags.occ_percent::cpu01.data 0.003898 # Average percentage of cache occupancy system.cpu01.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu01.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu01.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu01.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu01.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu01.dcache.tags.data_accesses 210 # Number of data accesses system.cpu01.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu01.dcache.ReadReq_hits::switch_cpus01.data 50 # number of ReadReq hits system.cpu01.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu01.dcache.demand_hits::switch_cpus01.data 50 # number of demand (read+write) hits system.cpu01.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu01.dcache.overall_hits::switch_cpus01.data 50 # number of overall hits system.cpu01.dcache.overall_hits::total 50 # number of overall hits system.cpu01.dcache.ReadReq_misses::cpu01.data 2 # number of ReadReq misses system.cpu01.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu01.dcache.demand_misses::cpu01.data 2 # number of demand (read+write) misses system.cpu01.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu01.dcache.overall_misses::cpu01.data 2 # number of overall misses system.cpu01.dcache.overall_misses::total 2 # number of overall misses system.cpu01.dcache.ReadReq_miss_latency::cpu01.data 371000 # number of ReadReq miss cycles system.cpu01.dcache.ReadReq_miss_latency::total 371000 # number of ReadReq miss cycles system.cpu01.dcache.demand_miss_latency::cpu01.data 371000 # number of demand (read+write) miss cycles system.cpu01.dcache.demand_miss_latency::total 371000 # number of demand (read+write) miss cycles system.cpu01.dcache.overall_miss_latency::cpu01.data 371000 # number of overall miss cycles system.cpu01.dcache.overall_miss_latency::total 371000 # number of overall miss cycles system.cpu01.dcache.ReadReq_accesses::cpu01.data 2 # number of ReadReq accesses(hits+misses) system.cpu01.dcache.ReadReq_accesses::switch_cpus01.data 50 # number of ReadReq accesses(hits+misses) system.cpu01.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu01.dcache.demand_accesses::cpu01.data 2 # number of demand (read+write) accesses system.cpu01.dcache.demand_accesses::switch_cpus01.data 50 # number of demand (read+write) accesses system.cpu01.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu01.dcache.overall_accesses::cpu01.data 2 # number of overall (read+write) accesses system.cpu01.dcache.overall_accesses::switch_cpus01.data 50 # number of overall (read+write) accesses system.cpu01.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu01.dcache.ReadReq_miss_rate::cpu01.data 1 # miss rate for ReadReq accesses system.cpu01.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu01.dcache.demand_miss_rate::cpu01.data 1 # miss rate for demand accesses system.cpu01.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu01.dcache.overall_miss_rate::cpu01.data 1 # miss rate for overall accesses system.cpu01.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu01.dcache.ReadReq_avg_miss_latency::cpu01.data 185500 # average ReadReq miss latency system.cpu01.dcache.ReadReq_avg_miss_latency::total 185500 # average ReadReq miss latency system.cpu01.dcache.demand_avg_miss_latency::cpu01.data 185500 # average overall miss latency system.cpu01.dcache.demand_avg_miss_latency::total 185500 # average overall miss latency system.cpu01.dcache.overall_avg_miss_latency::cpu01.data 185500 # average overall miss latency system.cpu01.dcache.overall_avg_miss_latency::total 185500 # average overall miss latency system.cpu01.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu01.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu01.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu01.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu01.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu01.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu01.dcache.ReadReq_mshr_misses::cpu01.data 2 # number of ReadReq MSHR misses system.cpu01.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu01.dcache.demand_mshr_misses::cpu01.data 2 # number of demand (read+write) MSHR misses system.cpu01.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu01.dcache.overall_mshr_misses::cpu01.data 2 # number of overall MSHR misses system.cpu01.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu01.dcache.ReadReq_mshr_miss_latency::cpu01.data 369000 # number of ReadReq MSHR miss cycles system.cpu01.dcache.ReadReq_mshr_miss_latency::total 369000 # number of ReadReq MSHR miss cycles system.cpu01.dcache.demand_mshr_miss_latency::cpu01.data 369000 # number of demand (read+write) MSHR miss cycles system.cpu01.dcache.demand_mshr_miss_latency::total 369000 # number of demand (read+write) MSHR miss cycles system.cpu01.dcache.overall_mshr_miss_latency::cpu01.data 369000 # number of overall MSHR miss cycles system.cpu01.dcache.overall_mshr_miss_latency::total 369000 # number of overall MSHR miss cycles system.cpu01.dcache.ReadReq_mshr_miss_rate::cpu01.data 1 # mshr miss rate for ReadReq accesses system.cpu01.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu01.dcache.demand_mshr_miss_rate::cpu01.data 1 # mshr miss rate for demand accesses system.cpu01.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu01.dcache.overall_mshr_miss_rate::cpu01.data 1 # mshr miss rate for overall accesses system.cpu01.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu01.dcache.ReadReq_avg_mshr_miss_latency::cpu01.data 184500 # average ReadReq mshr miss latency system.cpu01.dcache.ReadReq_avg_mshr_miss_latency::total 184500 # average ReadReq mshr miss latency system.cpu01.dcache.demand_avg_mshr_miss_latency::cpu01.data 184500 # average overall mshr miss latency system.cpu01.dcache.demand_avg_mshr_miss_latency::total 184500 # average overall mshr miss latency system.cpu01.dcache.overall_avg_mshr_miss_latency::cpu01.data 184500 # average overall mshr miss latency system.cpu01.dcache.overall_avg_mshr_miss_latency::total 184500 # average overall mshr miss latency system.cpu01.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu01.icache.tags.replacements 0 # number of replacements system.cpu01.icache.tags.tagsinuse 1.995857 # Cycle average of tags in use system.cpu01.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu01.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu01.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu01.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu01.icache.tags.occ_blocks::cpu01.inst 1.995857 # Average occupied blocks per requestor system.cpu01.icache.tags.occ_percent::cpu01.inst 0.003898 # Average percentage of cache occupancy system.cpu01.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu01.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu01.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu01.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu01.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu01.icache.tags.data_accesses 622 # Number of data accesses system.cpu01.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu01.icache.ReadReq_hits::cpu01.inst 1 # number of ReadReq hits system.cpu01.icache.ReadReq_hits::switch_cpus01.inst 152 # number of ReadReq hits system.cpu01.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu01.icache.demand_hits::cpu01.inst 1 # number of demand (read+write) hits system.cpu01.icache.demand_hits::switch_cpus01.inst 152 # number of demand (read+write) hits system.cpu01.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu01.icache.overall_hits::cpu01.inst 1 # number of overall hits system.cpu01.icache.overall_hits::switch_cpus01.inst 152 # number of overall hits system.cpu01.icache.overall_hits::total 153 # number of overall hits system.cpu01.icache.ReadReq_misses::cpu01.inst 2 # number of ReadReq misses system.cpu01.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu01.icache.demand_misses::cpu01.inst 2 # number of demand (read+write) misses system.cpu01.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu01.icache.overall_misses::cpu01.inst 2 # number of overall misses system.cpu01.icache.overall_misses::total 2 # number of overall misses system.cpu01.icache.ReadReq_miss_latency::cpu01.inst 173000 # number of ReadReq miss cycles system.cpu01.icache.ReadReq_miss_latency::total 173000 # number of ReadReq miss cycles system.cpu01.icache.demand_miss_latency::cpu01.inst 173000 # number of demand (read+write) miss cycles system.cpu01.icache.demand_miss_latency::total 173000 # number of demand (read+write) miss cycles system.cpu01.icache.overall_miss_latency::cpu01.inst 173000 # number of overall miss cycles system.cpu01.icache.overall_miss_latency::total 173000 # number of overall miss cycles system.cpu01.icache.ReadReq_accesses::cpu01.inst 3 # number of ReadReq accesses(hits+misses) system.cpu01.icache.ReadReq_accesses::switch_cpus01.inst 152 # number of ReadReq accesses(hits+misses) system.cpu01.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu01.icache.demand_accesses::cpu01.inst 3 # number of demand (read+write) accesses system.cpu01.icache.demand_accesses::switch_cpus01.inst 152 # number of demand (read+write) accesses system.cpu01.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu01.icache.overall_accesses::cpu01.inst 3 # number of overall (read+write) accesses system.cpu01.icache.overall_accesses::switch_cpus01.inst 152 # number of overall (read+write) accesses system.cpu01.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu01.icache.ReadReq_miss_rate::cpu01.inst 0.666667 # miss rate for ReadReq accesses system.cpu01.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu01.icache.demand_miss_rate::cpu01.inst 0.666667 # miss rate for demand accesses system.cpu01.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu01.icache.overall_miss_rate::cpu01.inst 0.666667 # miss rate for overall accesses system.cpu01.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu01.icache.ReadReq_avg_miss_latency::cpu01.inst 86500 # average ReadReq miss latency system.cpu01.icache.ReadReq_avg_miss_latency::total 86500 # average ReadReq miss latency system.cpu01.icache.demand_avg_miss_latency::cpu01.inst 86500 # average overall miss latency system.cpu01.icache.demand_avg_miss_latency::total 86500 # average overall miss latency system.cpu01.icache.overall_avg_miss_latency::cpu01.inst 86500 # average overall miss latency system.cpu01.icache.overall_avg_miss_latency::total 86500 # average overall miss latency system.cpu01.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu01.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu01.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu01.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu01.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu01.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu01.icache.ReadReq_mshr_misses::cpu01.inst 2 # number of ReadReq MSHR misses system.cpu01.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu01.icache.demand_mshr_misses::cpu01.inst 2 # number of demand (read+write) MSHR misses system.cpu01.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu01.icache.overall_mshr_misses::cpu01.inst 2 # number of overall MSHR misses system.cpu01.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu01.icache.ReadReq_mshr_miss_latency::cpu01.inst 171000 # number of ReadReq MSHR miss cycles system.cpu01.icache.ReadReq_mshr_miss_latency::total 171000 # number of ReadReq MSHR miss cycles system.cpu01.icache.demand_mshr_miss_latency::cpu01.inst 171000 # number of demand (read+write) MSHR miss cycles system.cpu01.icache.demand_mshr_miss_latency::total 171000 # number of demand (read+write) MSHR miss cycles system.cpu01.icache.overall_mshr_miss_latency::cpu01.inst 171000 # number of overall MSHR miss cycles system.cpu01.icache.overall_mshr_miss_latency::total 171000 # number of overall MSHR miss cycles system.cpu01.icache.ReadReq_mshr_miss_rate::cpu01.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu01.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu01.icache.demand_mshr_miss_rate::cpu01.inst 0.666667 # mshr miss rate for demand accesses system.cpu01.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu01.icache.overall_mshr_miss_rate::cpu01.inst 0.666667 # mshr miss rate for overall accesses system.cpu01.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu01.icache.ReadReq_avg_mshr_miss_latency::cpu01.inst 85500 # average ReadReq mshr miss latency system.cpu01.icache.ReadReq_avg_mshr_miss_latency::total 85500 # average ReadReq mshr miss latency system.cpu01.icache.demand_avg_mshr_miss_latency::cpu01.inst 85500 # average overall mshr miss latency system.cpu01.icache.demand_avg_mshr_miss_latency::total 85500 # average overall mshr miss latency system.cpu01.icache.overall_avg_mshr_miss_latency::cpu01.inst 85500 # average overall mshr miss latency system.cpu01.icache.overall_avg_mshr_miss_latency::total 85500 # average overall mshr miss latency system.cpu02.branchPred.lookups 5 # Number of BP lookups system.cpu02.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu02.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu02.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu02.branchPred.BTBHits 0 # Number of BTB hits system.cpu02.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu02.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu02.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu02.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu02.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu02.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu02.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu02.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu02.dtb.fetch_hits 0 # ITB hits system.cpu02.dtb.fetch_misses 0 # ITB misses system.cpu02.dtb.fetch_acv 0 # ITB acv system.cpu02.dtb.fetch_accesses 0 # ITB accesses system.cpu02.dtb.read_hits 2 # DTB read hits system.cpu02.dtb.read_misses 0 # DTB read misses system.cpu02.dtb.read_acv 0 # DTB read access violations system.cpu02.dtb.read_accesses 0 # DTB read accesses system.cpu02.dtb.write_hits 0 # DTB write hits system.cpu02.dtb.write_misses 0 # DTB write misses system.cpu02.dtb.write_acv 0 # DTB write access violations system.cpu02.dtb.write_accesses 0 # DTB write accesses system.cpu02.dtb.data_hits 2 # DTB hits system.cpu02.dtb.data_misses 0 # DTB misses system.cpu02.dtb.data_acv 0 # DTB access violations system.cpu02.dtb.data_accesses 0 # DTB accesses system.cpu02.itb.fetch_hits 0 # ITB hits system.cpu02.itb.fetch_misses 1 # ITB misses system.cpu02.itb.fetch_acv 0 # ITB acv system.cpu02.itb.fetch_accesses 1 # ITB accesses system.cpu02.itb.read_hits 0 # DTB read hits system.cpu02.itb.read_misses 0 # DTB read misses system.cpu02.itb.read_acv 0 # DTB read access violations system.cpu02.itb.read_accesses 0 # DTB read accesses system.cpu02.itb.write_hits 0 # DTB write hits system.cpu02.itb.write_misses 0 # DTB write misses system.cpu02.itb.write_acv 0 # DTB write access violations system.cpu02.itb.write_accesses 0 # DTB write accesses system.cpu02.itb.data_hits 0 # DTB hits system.cpu02.itb.data_misses 0 # DTB misses system.cpu02.itb.data_acv 0 # DTB access violations system.cpu02.itb.data_accesses 0 # DTB accesses system.cpu02.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu02.numCycles 621 # number of cpu cycles simulated system.cpu02.numWorkItemsStarted 0 # number of work items this cpu started system.cpu02.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu02.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu02.fetch.Insts 10 # Number of instructions fetch has processed system.cpu02.fetch.Branches 5 # Number of branches that fetch encountered system.cpu02.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu02.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu02.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu02.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu02.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu02.fetch.CacheLines 3 # Number of cache lines fetched system.cpu02.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu02.fetch.branchRate 0.008052 # Number of branch fetches per cycle system.cpu02.fetch.rate 0.016103 # Number of inst fetches per cycle system.cpu02.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu02.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu02.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu02.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu02.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu02.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu02.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu02.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu02.rename.RunCycles 0 # Number of cycles rename is running system.cpu02.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu02.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu02.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu02.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu02.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu02.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu02.rename.serializingInsts 0 # count of serializing insts renamed system.cpu02.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu02.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu02.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu02.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu02.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu02.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu02.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu02.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu02.iq.iqInstsIssued 6 # Number of instructions issued system.cpu02.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu02.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu02.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu02.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu02.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu02.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu02.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu02.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu02.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu02.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu02.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu02.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu02.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu02.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu02.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu02.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu02.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu02.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu02.iq.FU_type_0::total 6 # Type of FU issued system.cpu02.iq.rate 0.009662 # Inst issue rate system.cpu02.iq.fu_busy_cnt 0 # FU busy when requested system.cpu02.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu02.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu02.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu02.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu02.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu02.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu02.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu02.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu02.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu02.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu02.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu02.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu02.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu02.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu02.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu02.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu02.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu02.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu02.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu02.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu02.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu02.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu02.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu02.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu02.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu02.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu02.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu02.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu02.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu02.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu02.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu02.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu02.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu02.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu02.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu02.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu02.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu02.iew.exec_swp 0 # number of swp insts executed system.cpu02.iew.exec_nop 1 # number of nop insts executed system.cpu02.iew.exec_refs 2 # number of memory reference insts executed system.cpu02.iew.exec_branches 1 # Number of branches executed system.cpu02.iew.exec_stores 0 # Number of stores executed system.cpu02.iew.exec_rate 0.009662 # Inst execution rate system.cpu02.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu02.iew.wb_count 5 # cumulative count of insts written-back system.cpu02.iew.wb_producers 1 # num instructions producing a value system.cpu02.iew.wb_consumers 1 # num instructions consuming a value system.cpu02.iew.wb_rate 0.008052 # insts written-back per cycle system.cpu02.iew.wb_fanout 1 # average fanout of values written-back system.cpu02.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu02.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu02.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu02.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu02.commit.committedInsts 1 # Number of instructions committed system.cpu02.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu02.commit.swp_count 0 # Number of s/w prefetches committed system.cpu02.commit.refs 1 # Number of memory references committed system.cpu02.commit.loads 1 # Number of loads committed system.cpu02.commit.membars 0 # Number of memory barriers committed system.cpu02.commit.branches 0 # Number of branches committed system.cpu02.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu02.commit.int_insts 1 # Number of committed integer instructions. system.cpu02.commit.function_calls 0 # Number of function calls committed. system.cpu02.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu02.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu02.commit.op_class_0::total 1 # Class of committed instruction system.cpu02.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu02.rob.rob_reads 60 # The number of ROB reads system.cpu02.rob.rob_writes 26 # The number of ROB writes system.cpu02.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu02.idleCycles 567 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu02.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu02.committedInsts 1 # Number of Instructions Simulated system.cpu02.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu02.cpi 621.000000 # CPI: Cycles Per Instruction system.cpu02.cpi_total 621.000000 # CPI: Total CPI of All Threads system.cpu02.ipc 0.001610 # IPC: Instructions Per Cycle system.cpu02.ipc_total 0.001610 # IPC: Total IPC of All Threads system.cpu02.int_regfile_reads 48 # number of integer regfile reads system.cpu02.int_regfile_writes 4 # number of integer regfile writes system.cpu02.fp_regfile_reads 32 # number of floating regfile reads system.cpu02.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu02.dcache.tags.replacements 0 # number of replacements system.cpu02.dcache.tags.tagsinuse 1.995821 # Cycle average of tags in use system.cpu02.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu02.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu02.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu02.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu02.dcache.tags.occ_blocks::cpu02.data 1.995821 # Average occupied blocks per requestor system.cpu02.dcache.tags.occ_percent::cpu02.data 0.003898 # Average percentage of cache occupancy system.cpu02.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu02.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu02.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu02.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu02.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu02.dcache.tags.data_accesses 210 # Number of data accesses system.cpu02.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu02.dcache.ReadReq_hits::switch_cpus02.data 50 # number of ReadReq hits system.cpu02.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu02.dcache.demand_hits::switch_cpus02.data 50 # number of demand (read+write) hits system.cpu02.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu02.dcache.overall_hits::switch_cpus02.data 50 # number of overall hits system.cpu02.dcache.overall_hits::total 50 # number of overall hits system.cpu02.dcache.ReadReq_misses::cpu02.data 2 # number of ReadReq misses system.cpu02.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu02.dcache.demand_misses::cpu02.data 2 # number of demand (read+write) misses system.cpu02.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu02.dcache.overall_misses::cpu02.data 2 # number of overall misses system.cpu02.dcache.overall_misses::total 2 # number of overall misses system.cpu02.dcache.ReadReq_miss_latency::cpu02.data 361500 # number of ReadReq miss cycles system.cpu02.dcache.ReadReq_miss_latency::total 361500 # number of ReadReq miss cycles system.cpu02.dcache.demand_miss_latency::cpu02.data 361500 # number of demand (read+write) miss cycles system.cpu02.dcache.demand_miss_latency::total 361500 # number of demand (read+write) miss cycles system.cpu02.dcache.overall_miss_latency::cpu02.data 361500 # number of overall miss cycles system.cpu02.dcache.overall_miss_latency::total 361500 # number of overall miss cycles system.cpu02.dcache.ReadReq_accesses::cpu02.data 2 # number of ReadReq accesses(hits+misses) system.cpu02.dcache.ReadReq_accesses::switch_cpus02.data 50 # number of ReadReq accesses(hits+misses) system.cpu02.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu02.dcache.demand_accesses::cpu02.data 2 # number of demand (read+write) accesses system.cpu02.dcache.demand_accesses::switch_cpus02.data 50 # number of demand (read+write) accesses system.cpu02.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu02.dcache.overall_accesses::cpu02.data 2 # number of overall (read+write) accesses system.cpu02.dcache.overall_accesses::switch_cpus02.data 50 # number of overall (read+write) accesses system.cpu02.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu02.dcache.ReadReq_miss_rate::cpu02.data 1 # miss rate for ReadReq accesses system.cpu02.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu02.dcache.demand_miss_rate::cpu02.data 1 # miss rate for demand accesses system.cpu02.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu02.dcache.overall_miss_rate::cpu02.data 1 # miss rate for overall accesses system.cpu02.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu02.dcache.ReadReq_avg_miss_latency::cpu02.data 180750 # average ReadReq miss latency system.cpu02.dcache.ReadReq_avg_miss_latency::total 180750 # average ReadReq miss latency system.cpu02.dcache.demand_avg_miss_latency::cpu02.data 180750 # average overall miss latency system.cpu02.dcache.demand_avg_miss_latency::total 180750 # average overall miss latency system.cpu02.dcache.overall_avg_miss_latency::cpu02.data 180750 # average overall miss latency system.cpu02.dcache.overall_avg_miss_latency::total 180750 # average overall miss latency system.cpu02.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu02.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu02.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu02.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu02.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu02.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu02.dcache.ReadReq_mshr_misses::cpu02.data 2 # number of ReadReq MSHR misses system.cpu02.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu02.dcache.demand_mshr_misses::cpu02.data 2 # number of demand (read+write) MSHR misses system.cpu02.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu02.dcache.overall_mshr_misses::cpu02.data 2 # number of overall MSHR misses system.cpu02.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu02.dcache.ReadReq_mshr_miss_latency::cpu02.data 359500 # number of ReadReq MSHR miss cycles system.cpu02.dcache.ReadReq_mshr_miss_latency::total 359500 # number of ReadReq MSHR miss cycles system.cpu02.dcache.demand_mshr_miss_latency::cpu02.data 359500 # number of demand (read+write) MSHR miss cycles system.cpu02.dcache.demand_mshr_miss_latency::total 359500 # number of demand (read+write) MSHR miss cycles system.cpu02.dcache.overall_mshr_miss_latency::cpu02.data 359500 # number of overall MSHR miss cycles system.cpu02.dcache.overall_mshr_miss_latency::total 359500 # number of overall MSHR miss cycles system.cpu02.dcache.ReadReq_mshr_miss_rate::cpu02.data 1 # mshr miss rate for ReadReq accesses system.cpu02.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu02.dcache.demand_mshr_miss_rate::cpu02.data 1 # mshr miss rate for demand accesses system.cpu02.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu02.dcache.overall_mshr_miss_rate::cpu02.data 1 # mshr miss rate for overall accesses system.cpu02.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu02.dcache.ReadReq_avg_mshr_miss_latency::cpu02.data 179750 # average ReadReq mshr miss latency system.cpu02.dcache.ReadReq_avg_mshr_miss_latency::total 179750 # average ReadReq mshr miss latency system.cpu02.dcache.demand_avg_mshr_miss_latency::cpu02.data 179750 # average overall mshr miss latency system.cpu02.dcache.demand_avg_mshr_miss_latency::total 179750 # average overall mshr miss latency system.cpu02.dcache.overall_avg_mshr_miss_latency::cpu02.data 179750 # average overall mshr miss latency system.cpu02.dcache.overall_avg_mshr_miss_latency::total 179750 # average overall mshr miss latency system.cpu02.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu02.icache.tags.replacements 0 # number of replacements system.cpu02.icache.tags.tagsinuse 1.995857 # Cycle average of tags in use system.cpu02.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu02.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu02.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu02.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu02.icache.tags.occ_blocks::cpu02.inst 1.995857 # Average occupied blocks per requestor system.cpu02.icache.tags.occ_percent::cpu02.inst 0.003898 # Average percentage of cache occupancy system.cpu02.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu02.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu02.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu02.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu02.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu02.icache.tags.data_accesses 622 # Number of data accesses system.cpu02.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu02.icache.ReadReq_hits::cpu02.inst 1 # number of ReadReq hits system.cpu02.icache.ReadReq_hits::switch_cpus02.inst 152 # number of ReadReq hits system.cpu02.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu02.icache.demand_hits::cpu02.inst 1 # number of demand (read+write) hits system.cpu02.icache.demand_hits::switch_cpus02.inst 152 # number of demand (read+write) hits system.cpu02.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu02.icache.overall_hits::cpu02.inst 1 # number of overall hits system.cpu02.icache.overall_hits::switch_cpus02.inst 152 # number of overall hits system.cpu02.icache.overall_hits::total 153 # number of overall hits system.cpu02.icache.ReadReq_misses::cpu02.inst 2 # number of ReadReq misses system.cpu02.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu02.icache.demand_misses::cpu02.inst 2 # number of demand (read+write) misses system.cpu02.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu02.icache.overall_misses::cpu02.inst 2 # number of overall misses system.cpu02.icache.overall_misses::total 2 # number of overall misses system.cpu02.icache.ReadReq_miss_latency::cpu02.inst 172500 # number of ReadReq miss cycles system.cpu02.icache.ReadReq_miss_latency::total 172500 # number of ReadReq miss cycles system.cpu02.icache.demand_miss_latency::cpu02.inst 172500 # number of demand (read+write) miss cycles system.cpu02.icache.demand_miss_latency::total 172500 # number of demand (read+write) miss cycles system.cpu02.icache.overall_miss_latency::cpu02.inst 172500 # number of overall miss cycles system.cpu02.icache.overall_miss_latency::total 172500 # number of overall miss cycles system.cpu02.icache.ReadReq_accesses::cpu02.inst 3 # number of ReadReq accesses(hits+misses) system.cpu02.icache.ReadReq_accesses::switch_cpus02.inst 152 # number of ReadReq accesses(hits+misses) system.cpu02.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu02.icache.demand_accesses::cpu02.inst 3 # number of demand (read+write) accesses system.cpu02.icache.demand_accesses::switch_cpus02.inst 152 # number of demand (read+write) accesses system.cpu02.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu02.icache.overall_accesses::cpu02.inst 3 # number of overall (read+write) accesses system.cpu02.icache.overall_accesses::switch_cpus02.inst 152 # number of overall (read+write) accesses system.cpu02.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu02.icache.ReadReq_miss_rate::cpu02.inst 0.666667 # miss rate for ReadReq accesses system.cpu02.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu02.icache.demand_miss_rate::cpu02.inst 0.666667 # miss rate for demand accesses system.cpu02.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu02.icache.overall_miss_rate::cpu02.inst 0.666667 # miss rate for overall accesses system.cpu02.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu02.icache.ReadReq_avg_miss_latency::cpu02.inst 86250 # average ReadReq miss latency system.cpu02.icache.ReadReq_avg_miss_latency::total 86250 # average ReadReq miss latency system.cpu02.icache.demand_avg_miss_latency::cpu02.inst 86250 # average overall miss latency system.cpu02.icache.demand_avg_miss_latency::total 86250 # average overall miss latency system.cpu02.icache.overall_avg_miss_latency::cpu02.inst 86250 # average overall miss latency system.cpu02.icache.overall_avg_miss_latency::total 86250 # average overall miss latency system.cpu02.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu02.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu02.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu02.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu02.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu02.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu02.icache.ReadReq_mshr_misses::cpu02.inst 2 # number of ReadReq MSHR misses system.cpu02.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu02.icache.demand_mshr_misses::cpu02.inst 2 # number of demand (read+write) MSHR misses system.cpu02.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu02.icache.overall_mshr_misses::cpu02.inst 2 # number of overall MSHR misses system.cpu02.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu02.icache.ReadReq_mshr_miss_latency::cpu02.inst 170500 # number of ReadReq MSHR miss cycles system.cpu02.icache.ReadReq_mshr_miss_latency::total 170500 # number of ReadReq MSHR miss cycles system.cpu02.icache.demand_mshr_miss_latency::cpu02.inst 170500 # number of demand (read+write) MSHR miss cycles system.cpu02.icache.demand_mshr_miss_latency::total 170500 # number of demand (read+write) MSHR miss cycles system.cpu02.icache.overall_mshr_miss_latency::cpu02.inst 170500 # number of overall MSHR miss cycles system.cpu02.icache.overall_mshr_miss_latency::total 170500 # number of overall MSHR miss cycles system.cpu02.icache.ReadReq_mshr_miss_rate::cpu02.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu02.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu02.icache.demand_mshr_miss_rate::cpu02.inst 0.666667 # mshr miss rate for demand accesses system.cpu02.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu02.icache.overall_mshr_miss_rate::cpu02.inst 0.666667 # mshr miss rate for overall accesses system.cpu02.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu02.icache.ReadReq_avg_mshr_miss_latency::cpu02.inst 85250 # average ReadReq mshr miss latency system.cpu02.icache.ReadReq_avg_mshr_miss_latency::total 85250 # average ReadReq mshr miss latency system.cpu02.icache.demand_avg_mshr_miss_latency::cpu02.inst 85250 # average overall mshr miss latency system.cpu02.icache.demand_avg_mshr_miss_latency::total 85250 # average overall mshr miss latency system.cpu02.icache.overall_avg_mshr_miss_latency::cpu02.inst 85250 # average overall mshr miss latency system.cpu02.icache.overall_avg_mshr_miss_latency::total 85250 # average overall mshr miss latency system.cpu03.branchPred.lookups 5 # Number of BP lookups system.cpu03.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu03.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu03.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu03.branchPred.BTBHits 0 # Number of BTB hits system.cpu03.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu03.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu03.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu03.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu03.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu03.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu03.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu03.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu03.dtb.fetch_hits 0 # ITB hits system.cpu03.dtb.fetch_misses 0 # ITB misses system.cpu03.dtb.fetch_acv 0 # ITB acv system.cpu03.dtb.fetch_accesses 0 # ITB accesses system.cpu03.dtb.read_hits 2 # DTB read hits system.cpu03.dtb.read_misses 0 # DTB read misses system.cpu03.dtb.read_acv 0 # DTB read access violations system.cpu03.dtb.read_accesses 0 # DTB read accesses system.cpu03.dtb.write_hits 0 # DTB write hits system.cpu03.dtb.write_misses 0 # DTB write misses system.cpu03.dtb.write_acv 0 # DTB write access violations system.cpu03.dtb.write_accesses 0 # DTB write accesses system.cpu03.dtb.data_hits 2 # DTB hits system.cpu03.dtb.data_misses 0 # DTB misses system.cpu03.dtb.data_acv 0 # DTB access violations system.cpu03.dtb.data_accesses 0 # DTB accesses system.cpu03.itb.fetch_hits 0 # ITB hits system.cpu03.itb.fetch_misses 1 # ITB misses system.cpu03.itb.fetch_acv 0 # ITB acv system.cpu03.itb.fetch_accesses 1 # ITB accesses system.cpu03.itb.read_hits 0 # DTB read hits system.cpu03.itb.read_misses 0 # DTB read misses system.cpu03.itb.read_acv 0 # DTB read access violations system.cpu03.itb.read_accesses 0 # DTB read accesses system.cpu03.itb.write_hits 0 # DTB write hits system.cpu03.itb.write_misses 0 # DTB write misses system.cpu03.itb.write_acv 0 # DTB write access violations system.cpu03.itb.write_accesses 0 # DTB write accesses system.cpu03.itb.data_hits 0 # DTB hits system.cpu03.itb.data_misses 0 # DTB misses system.cpu03.itb.data_acv 0 # DTB access violations system.cpu03.itb.data_accesses 0 # DTB accesses system.cpu03.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu03.numCycles 631 # number of cpu cycles simulated system.cpu03.numWorkItemsStarted 0 # number of work items this cpu started system.cpu03.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu03.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu03.fetch.Insts 10 # Number of instructions fetch has processed system.cpu03.fetch.Branches 5 # Number of branches that fetch encountered system.cpu03.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu03.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu03.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu03.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu03.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu03.fetch.CacheLines 3 # Number of cache lines fetched system.cpu03.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu03.fetch.branchRate 0.007924 # Number of branch fetches per cycle system.cpu03.fetch.rate 0.015848 # Number of inst fetches per cycle system.cpu03.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu03.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu03.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu03.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu03.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu03.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu03.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu03.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu03.rename.RunCycles 0 # Number of cycles rename is running system.cpu03.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu03.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu03.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu03.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu03.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu03.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu03.rename.serializingInsts 0 # count of serializing insts renamed system.cpu03.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu03.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu03.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu03.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu03.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu03.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu03.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu03.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu03.iq.iqInstsIssued 6 # Number of instructions issued system.cpu03.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu03.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu03.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu03.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu03.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu03.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu03.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu03.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu03.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu03.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu03.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu03.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu03.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu03.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu03.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu03.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu03.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu03.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu03.iq.FU_type_0::total 6 # Type of FU issued system.cpu03.iq.rate 0.009509 # Inst issue rate system.cpu03.iq.fu_busy_cnt 0 # FU busy when requested system.cpu03.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu03.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu03.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu03.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu03.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu03.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu03.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu03.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu03.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu03.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu03.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu03.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu03.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu03.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu03.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu03.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu03.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu03.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu03.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu03.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu03.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu03.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu03.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu03.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu03.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu03.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu03.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu03.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu03.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu03.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu03.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu03.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu03.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu03.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu03.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu03.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu03.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu03.iew.exec_swp 0 # number of swp insts executed system.cpu03.iew.exec_nop 1 # number of nop insts executed system.cpu03.iew.exec_refs 2 # number of memory reference insts executed system.cpu03.iew.exec_branches 1 # Number of branches executed system.cpu03.iew.exec_stores 0 # Number of stores executed system.cpu03.iew.exec_rate 0.009509 # Inst execution rate system.cpu03.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu03.iew.wb_count 5 # cumulative count of insts written-back system.cpu03.iew.wb_producers 1 # num instructions producing a value system.cpu03.iew.wb_consumers 1 # num instructions consuming a value system.cpu03.iew.wb_rate 0.007924 # insts written-back per cycle system.cpu03.iew.wb_fanout 1 # average fanout of values written-back system.cpu03.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu03.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu03.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu03.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu03.commit.committedInsts 1 # Number of instructions committed system.cpu03.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu03.commit.swp_count 0 # Number of s/w prefetches committed system.cpu03.commit.refs 1 # Number of memory references committed system.cpu03.commit.loads 1 # Number of loads committed system.cpu03.commit.membars 0 # Number of memory barriers committed system.cpu03.commit.branches 0 # Number of branches committed system.cpu03.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu03.commit.int_insts 1 # Number of committed integer instructions. system.cpu03.commit.function_calls 0 # Number of function calls committed. system.cpu03.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu03.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu03.commit.op_class_0::total 1 # Class of committed instruction system.cpu03.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu03.rob.rob_reads 60 # The number of ROB reads system.cpu03.rob.rob_writes 26 # The number of ROB writes system.cpu03.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu03.idleCycles 577 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu03.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu03.committedInsts 1 # Number of Instructions Simulated system.cpu03.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu03.cpi 631.000000 # CPI: Cycles Per Instruction system.cpu03.cpi_total 631.000000 # CPI: Total CPI of All Threads system.cpu03.ipc 0.001585 # IPC: Instructions Per Cycle system.cpu03.ipc_total 0.001585 # IPC: Total IPC of All Threads system.cpu03.int_regfile_reads 48 # number of integer regfile reads system.cpu03.int_regfile_writes 4 # number of integer regfile writes system.cpu03.fp_regfile_reads 32 # number of floating regfile reads system.cpu03.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu03.dcache.tags.replacements 0 # number of replacements system.cpu03.dcache.tags.tagsinuse 1.995820 # Cycle average of tags in use system.cpu03.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu03.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu03.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu03.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu03.dcache.tags.occ_blocks::cpu03.data 1.995820 # Average occupied blocks per requestor system.cpu03.dcache.tags.occ_percent::cpu03.data 0.003898 # Average percentage of cache occupancy system.cpu03.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu03.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu03.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu03.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu03.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu03.dcache.tags.data_accesses 210 # Number of data accesses system.cpu03.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu03.dcache.ReadReq_hits::switch_cpus03.data 50 # number of ReadReq hits system.cpu03.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu03.dcache.demand_hits::switch_cpus03.data 50 # number of demand (read+write) hits system.cpu03.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu03.dcache.overall_hits::switch_cpus03.data 50 # number of overall hits system.cpu03.dcache.overall_hits::total 50 # number of overall hits system.cpu03.dcache.ReadReq_misses::cpu03.data 2 # number of ReadReq misses system.cpu03.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu03.dcache.demand_misses::cpu03.data 2 # number of demand (read+write) misses system.cpu03.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu03.dcache.overall_misses::cpu03.data 2 # number of overall misses system.cpu03.dcache.overall_misses::total 2 # number of overall misses system.cpu03.dcache.ReadReq_miss_latency::cpu03.data 367000 # number of ReadReq miss cycles system.cpu03.dcache.ReadReq_miss_latency::total 367000 # number of ReadReq miss cycles system.cpu03.dcache.demand_miss_latency::cpu03.data 367000 # number of demand (read+write) miss cycles system.cpu03.dcache.demand_miss_latency::total 367000 # number of demand (read+write) miss cycles system.cpu03.dcache.overall_miss_latency::cpu03.data 367000 # number of overall miss cycles system.cpu03.dcache.overall_miss_latency::total 367000 # number of overall miss cycles system.cpu03.dcache.ReadReq_accesses::cpu03.data 2 # number of ReadReq accesses(hits+misses) system.cpu03.dcache.ReadReq_accesses::switch_cpus03.data 50 # number of ReadReq accesses(hits+misses) system.cpu03.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu03.dcache.demand_accesses::cpu03.data 2 # number of demand (read+write) accesses system.cpu03.dcache.demand_accesses::switch_cpus03.data 50 # number of demand (read+write) accesses system.cpu03.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu03.dcache.overall_accesses::cpu03.data 2 # number of overall (read+write) accesses system.cpu03.dcache.overall_accesses::switch_cpus03.data 50 # number of overall (read+write) accesses system.cpu03.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu03.dcache.ReadReq_miss_rate::cpu03.data 1 # miss rate for ReadReq accesses system.cpu03.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu03.dcache.demand_miss_rate::cpu03.data 1 # miss rate for demand accesses system.cpu03.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu03.dcache.overall_miss_rate::cpu03.data 1 # miss rate for overall accesses system.cpu03.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu03.dcache.ReadReq_avg_miss_latency::cpu03.data 183500 # average ReadReq miss latency system.cpu03.dcache.ReadReq_avg_miss_latency::total 183500 # average ReadReq miss latency system.cpu03.dcache.demand_avg_miss_latency::cpu03.data 183500 # average overall miss latency system.cpu03.dcache.demand_avg_miss_latency::total 183500 # average overall miss latency system.cpu03.dcache.overall_avg_miss_latency::cpu03.data 183500 # average overall miss latency system.cpu03.dcache.overall_avg_miss_latency::total 183500 # average overall miss latency system.cpu03.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu03.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu03.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu03.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu03.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu03.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu03.dcache.ReadReq_mshr_misses::cpu03.data 2 # number of ReadReq MSHR misses system.cpu03.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu03.dcache.demand_mshr_misses::cpu03.data 2 # number of demand (read+write) MSHR misses system.cpu03.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu03.dcache.overall_mshr_misses::cpu03.data 2 # number of overall MSHR misses system.cpu03.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu03.dcache.ReadReq_mshr_miss_latency::cpu03.data 365000 # number of ReadReq MSHR miss cycles system.cpu03.dcache.ReadReq_mshr_miss_latency::total 365000 # number of ReadReq MSHR miss cycles system.cpu03.dcache.demand_mshr_miss_latency::cpu03.data 365000 # number of demand (read+write) MSHR miss cycles system.cpu03.dcache.demand_mshr_miss_latency::total 365000 # number of demand (read+write) MSHR miss cycles system.cpu03.dcache.overall_mshr_miss_latency::cpu03.data 365000 # number of overall MSHR miss cycles system.cpu03.dcache.overall_mshr_miss_latency::total 365000 # number of overall MSHR miss cycles system.cpu03.dcache.ReadReq_mshr_miss_rate::cpu03.data 1 # mshr miss rate for ReadReq accesses system.cpu03.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu03.dcache.demand_mshr_miss_rate::cpu03.data 1 # mshr miss rate for demand accesses system.cpu03.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu03.dcache.overall_mshr_miss_rate::cpu03.data 1 # mshr miss rate for overall accesses system.cpu03.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu03.dcache.ReadReq_avg_mshr_miss_latency::cpu03.data 182500 # average ReadReq mshr miss latency system.cpu03.dcache.ReadReq_avg_mshr_miss_latency::total 182500 # average ReadReq mshr miss latency system.cpu03.dcache.demand_avg_mshr_miss_latency::cpu03.data 182500 # average overall mshr miss latency system.cpu03.dcache.demand_avg_mshr_miss_latency::total 182500 # average overall mshr miss latency system.cpu03.dcache.overall_avg_mshr_miss_latency::cpu03.data 182500 # average overall mshr miss latency system.cpu03.dcache.overall_avg_mshr_miss_latency::total 182500 # average overall mshr miss latency system.cpu03.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu03.icache.tags.replacements 0 # number of replacements system.cpu03.icache.tags.tagsinuse 1.995857 # Cycle average of tags in use system.cpu03.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu03.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu03.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu03.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu03.icache.tags.occ_blocks::cpu03.inst 1.995857 # Average occupied blocks per requestor system.cpu03.icache.tags.occ_percent::cpu03.inst 0.003898 # Average percentage of cache occupancy system.cpu03.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu03.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu03.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu03.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu03.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu03.icache.tags.data_accesses 622 # Number of data accesses system.cpu03.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu03.icache.ReadReq_hits::cpu03.inst 1 # number of ReadReq hits system.cpu03.icache.ReadReq_hits::switch_cpus03.inst 152 # number of ReadReq hits system.cpu03.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu03.icache.demand_hits::cpu03.inst 1 # number of demand (read+write) hits system.cpu03.icache.demand_hits::switch_cpus03.inst 152 # number of demand (read+write) hits system.cpu03.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu03.icache.overall_hits::cpu03.inst 1 # number of overall hits system.cpu03.icache.overall_hits::switch_cpus03.inst 152 # number of overall hits system.cpu03.icache.overall_hits::total 153 # number of overall hits system.cpu03.icache.ReadReq_misses::cpu03.inst 2 # number of ReadReq misses system.cpu03.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu03.icache.demand_misses::cpu03.inst 2 # number of demand (read+write) misses system.cpu03.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu03.icache.overall_misses::cpu03.inst 2 # number of overall misses system.cpu03.icache.overall_misses::total 2 # number of overall misses system.cpu03.icache.ReadReq_miss_latency::cpu03.inst 172000 # number of ReadReq miss cycles system.cpu03.icache.ReadReq_miss_latency::total 172000 # number of ReadReq miss cycles system.cpu03.icache.demand_miss_latency::cpu03.inst 172000 # number of demand (read+write) miss cycles system.cpu03.icache.demand_miss_latency::total 172000 # number of demand (read+write) miss cycles system.cpu03.icache.overall_miss_latency::cpu03.inst 172000 # number of overall miss cycles system.cpu03.icache.overall_miss_latency::total 172000 # number of overall miss cycles system.cpu03.icache.ReadReq_accesses::cpu03.inst 3 # number of ReadReq accesses(hits+misses) system.cpu03.icache.ReadReq_accesses::switch_cpus03.inst 152 # number of ReadReq accesses(hits+misses) system.cpu03.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu03.icache.demand_accesses::cpu03.inst 3 # number of demand (read+write) accesses system.cpu03.icache.demand_accesses::switch_cpus03.inst 152 # number of demand (read+write) accesses system.cpu03.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu03.icache.overall_accesses::cpu03.inst 3 # number of overall (read+write) accesses system.cpu03.icache.overall_accesses::switch_cpus03.inst 152 # number of overall (read+write) accesses system.cpu03.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu03.icache.ReadReq_miss_rate::cpu03.inst 0.666667 # miss rate for ReadReq accesses system.cpu03.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu03.icache.demand_miss_rate::cpu03.inst 0.666667 # miss rate for demand accesses system.cpu03.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu03.icache.overall_miss_rate::cpu03.inst 0.666667 # miss rate for overall accesses system.cpu03.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu03.icache.ReadReq_avg_miss_latency::cpu03.inst 86000 # average ReadReq miss latency system.cpu03.icache.ReadReq_avg_miss_latency::total 86000 # average ReadReq miss latency system.cpu03.icache.demand_avg_miss_latency::cpu03.inst 86000 # average overall miss latency system.cpu03.icache.demand_avg_miss_latency::total 86000 # average overall miss latency system.cpu03.icache.overall_avg_miss_latency::cpu03.inst 86000 # average overall miss latency system.cpu03.icache.overall_avg_miss_latency::total 86000 # average overall miss latency system.cpu03.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu03.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu03.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu03.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu03.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu03.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu03.icache.ReadReq_mshr_misses::cpu03.inst 2 # number of ReadReq MSHR misses system.cpu03.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu03.icache.demand_mshr_misses::cpu03.inst 2 # number of demand (read+write) MSHR misses system.cpu03.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu03.icache.overall_mshr_misses::cpu03.inst 2 # number of overall MSHR misses system.cpu03.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu03.icache.ReadReq_mshr_miss_latency::cpu03.inst 170000 # number of ReadReq MSHR miss cycles system.cpu03.icache.ReadReq_mshr_miss_latency::total 170000 # number of ReadReq MSHR miss cycles system.cpu03.icache.demand_mshr_miss_latency::cpu03.inst 170000 # number of demand (read+write) MSHR miss cycles system.cpu03.icache.demand_mshr_miss_latency::total 170000 # number of demand (read+write) MSHR miss cycles system.cpu03.icache.overall_mshr_miss_latency::cpu03.inst 170000 # number of overall MSHR miss cycles system.cpu03.icache.overall_mshr_miss_latency::total 170000 # number of overall MSHR miss cycles system.cpu03.icache.ReadReq_mshr_miss_rate::cpu03.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu03.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu03.icache.demand_mshr_miss_rate::cpu03.inst 0.666667 # mshr miss rate for demand accesses system.cpu03.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu03.icache.overall_mshr_miss_rate::cpu03.inst 0.666667 # mshr miss rate for overall accesses system.cpu03.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu03.icache.ReadReq_avg_mshr_miss_latency::cpu03.inst 85000 # average ReadReq mshr miss latency system.cpu03.icache.ReadReq_avg_mshr_miss_latency::total 85000 # average ReadReq mshr miss latency system.cpu03.icache.demand_avg_mshr_miss_latency::cpu03.inst 85000 # average overall mshr miss latency system.cpu03.icache.demand_avg_mshr_miss_latency::total 85000 # average overall mshr miss latency system.cpu03.icache.overall_avg_mshr_miss_latency::cpu03.inst 85000 # average overall mshr miss latency system.cpu03.icache.overall_avg_mshr_miss_latency::total 85000 # average overall mshr miss latency system.cpu04.branchPred.lookups 5 # Number of BP lookups system.cpu04.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu04.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu04.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu04.branchPred.BTBHits 0 # Number of BTB hits system.cpu04.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu04.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu04.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu04.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu04.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu04.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu04.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu04.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu04.dtb.fetch_hits 0 # ITB hits system.cpu04.dtb.fetch_misses 0 # ITB misses system.cpu04.dtb.fetch_acv 0 # ITB acv system.cpu04.dtb.fetch_accesses 0 # ITB accesses system.cpu04.dtb.read_hits 2 # DTB read hits system.cpu04.dtb.read_misses 0 # DTB read misses system.cpu04.dtb.read_acv 0 # DTB read access violations system.cpu04.dtb.read_accesses 0 # DTB read accesses system.cpu04.dtb.write_hits 0 # DTB write hits system.cpu04.dtb.write_misses 0 # DTB write misses system.cpu04.dtb.write_acv 0 # DTB write access violations system.cpu04.dtb.write_accesses 0 # DTB write accesses system.cpu04.dtb.data_hits 2 # DTB hits system.cpu04.dtb.data_misses 0 # DTB misses system.cpu04.dtb.data_acv 0 # DTB access violations system.cpu04.dtb.data_accesses 0 # DTB accesses system.cpu04.itb.fetch_hits 0 # ITB hits system.cpu04.itb.fetch_misses 1 # ITB misses system.cpu04.itb.fetch_acv 0 # ITB acv system.cpu04.itb.fetch_accesses 1 # ITB accesses system.cpu04.itb.read_hits 0 # DTB read hits system.cpu04.itb.read_misses 0 # DTB read misses system.cpu04.itb.read_acv 0 # DTB read access violations system.cpu04.itb.read_accesses 0 # DTB read accesses system.cpu04.itb.write_hits 0 # DTB write hits system.cpu04.itb.write_misses 0 # DTB write misses system.cpu04.itb.write_acv 0 # DTB write access violations system.cpu04.itb.write_accesses 0 # DTB write accesses system.cpu04.itb.data_hits 0 # DTB hits system.cpu04.itb.data_misses 0 # DTB misses system.cpu04.itb.data_acv 0 # DTB access violations system.cpu04.itb.data_accesses 0 # DTB accesses system.cpu04.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu04.numCycles 511 # number of cpu cycles simulated system.cpu04.numWorkItemsStarted 0 # number of work items this cpu started system.cpu04.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu04.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu04.fetch.Insts 10 # Number of instructions fetch has processed system.cpu04.fetch.Branches 5 # Number of branches that fetch encountered system.cpu04.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu04.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu04.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu04.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu04.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu04.fetch.CacheLines 3 # Number of cache lines fetched system.cpu04.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu04.fetch.branchRate 0.009785 # Number of branch fetches per cycle system.cpu04.fetch.rate 0.019569 # Number of inst fetches per cycle system.cpu04.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu04.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu04.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu04.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu04.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu04.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu04.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu04.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu04.rename.RunCycles 0 # Number of cycles rename is running system.cpu04.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu04.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu04.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu04.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu04.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu04.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu04.rename.serializingInsts 0 # count of serializing insts renamed system.cpu04.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu04.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu04.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu04.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu04.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu04.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu04.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu04.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu04.iq.iqInstsIssued 6 # Number of instructions issued system.cpu04.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu04.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu04.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu04.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu04.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu04.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu04.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu04.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu04.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu04.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu04.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu04.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu04.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu04.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu04.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu04.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu04.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu04.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu04.iq.FU_type_0::total 6 # Type of FU issued system.cpu04.iq.rate 0.011742 # Inst issue rate system.cpu04.iq.fu_busy_cnt 0 # FU busy when requested system.cpu04.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu04.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu04.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu04.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu04.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu04.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu04.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu04.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu04.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu04.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu04.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu04.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu04.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu04.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu04.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu04.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu04.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu04.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu04.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu04.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu04.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu04.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu04.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu04.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu04.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu04.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu04.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu04.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu04.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu04.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu04.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu04.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu04.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu04.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu04.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu04.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu04.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu04.iew.exec_swp 0 # number of swp insts executed system.cpu04.iew.exec_nop 1 # number of nop insts executed system.cpu04.iew.exec_refs 2 # number of memory reference insts executed system.cpu04.iew.exec_branches 1 # Number of branches executed system.cpu04.iew.exec_stores 0 # Number of stores executed system.cpu04.iew.exec_rate 0.011742 # Inst execution rate system.cpu04.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu04.iew.wb_count 5 # cumulative count of insts written-back system.cpu04.iew.wb_producers 1 # num instructions producing a value system.cpu04.iew.wb_consumers 1 # num instructions consuming a value system.cpu04.iew.wb_rate 0.009785 # insts written-back per cycle system.cpu04.iew.wb_fanout 1 # average fanout of values written-back system.cpu04.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu04.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu04.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu04.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu04.commit.committedInsts 1 # Number of instructions committed system.cpu04.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu04.commit.swp_count 0 # Number of s/w prefetches committed system.cpu04.commit.refs 1 # Number of memory references committed system.cpu04.commit.loads 1 # Number of loads committed system.cpu04.commit.membars 0 # Number of memory barriers committed system.cpu04.commit.branches 0 # Number of branches committed system.cpu04.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu04.commit.int_insts 1 # Number of committed integer instructions. system.cpu04.commit.function_calls 0 # Number of function calls committed. system.cpu04.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu04.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu04.commit.op_class_0::total 1 # Class of committed instruction system.cpu04.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu04.rob.rob_reads 60 # The number of ROB reads system.cpu04.rob.rob_writes 26 # The number of ROB writes system.cpu04.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu04.idleCycles 457 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu04.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu04.committedInsts 1 # Number of Instructions Simulated system.cpu04.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu04.cpi 511.000000 # CPI: Cycles Per Instruction system.cpu04.cpi_total 511.000000 # CPI: Total CPI of All Threads system.cpu04.ipc 0.001957 # IPC: Instructions Per Cycle system.cpu04.ipc_total 0.001957 # IPC: Total IPC of All Threads system.cpu04.int_regfile_reads 48 # number of integer regfile reads system.cpu04.int_regfile_writes 4 # number of integer regfile writes system.cpu04.fp_regfile_reads 32 # number of floating regfile reads system.cpu04.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu04.dcache.tags.replacements 0 # number of replacements system.cpu04.dcache.tags.tagsinuse 1.995828 # Cycle average of tags in use system.cpu04.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu04.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu04.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu04.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu04.dcache.tags.occ_blocks::cpu04.data 1.995828 # Average occupied blocks per requestor system.cpu04.dcache.tags.occ_percent::cpu04.data 0.003898 # Average percentage of cache occupancy system.cpu04.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu04.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu04.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu04.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu04.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu04.dcache.tags.data_accesses 210 # Number of data accesses system.cpu04.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu04.dcache.ReadReq_hits::switch_cpus04.data 50 # number of ReadReq hits system.cpu04.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu04.dcache.demand_hits::switch_cpus04.data 50 # number of demand (read+write) hits system.cpu04.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu04.dcache.overall_hits::switch_cpus04.data 50 # number of overall hits system.cpu04.dcache.overall_hits::total 50 # number of overall hits system.cpu04.dcache.ReadReq_misses::cpu04.data 2 # number of ReadReq misses system.cpu04.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu04.dcache.demand_misses::cpu04.data 2 # number of demand (read+write) misses system.cpu04.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu04.dcache.overall_misses::cpu04.data 2 # number of overall misses system.cpu04.dcache.overall_misses::total 2 # number of overall misses system.cpu04.dcache.ReadReq_miss_latency::cpu04.data 314500 # number of ReadReq miss cycles system.cpu04.dcache.ReadReq_miss_latency::total 314500 # number of ReadReq miss cycles system.cpu04.dcache.demand_miss_latency::cpu04.data 314500 # number of demand (read+write) miss cycles system.cpu04.dcache.demand_miss_latency::total 314500 # number of demand (read+write) miss cycles system.cpu04.dcache.overall_miss_latency::cpu04.data 314500 # number of overall miss cycles system.cpu04.dcache.overall_miss_latency::total 314500 # number of overall miss cycles system.cpu04.dcache.ReadReq_accesses::cpu04.data 2 # number of ReadReq accesses(hits+misses) system.cpu04.dcache.ReadReq_accesses::switch_cpus04.data 50 # number of ReadReq accesses(hits+misses) system.cpu04.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu04.dcache.demand_accesses::cpu04.data 2 # number of demand (read+write) accesses system.cpu04.dcache.demand_accesses::switch_cpus04.data 50 # number of demand (read+write) accesses system.cpu04.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu04.dcache.overall_accesses::cpu04.data 2 # number of overall (read+write) accesses system.cpu04.dcache.overall_accesses::switch_cpus04.data 50 # number of overall (read+write) accesses system.cpu04.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu04.dcache.ReadReq_miss_rate::cpu04.data 1 # miss rate for ReadReq accesses system.cpu04.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu04.dcache.demand_miss_rate::cpu04.data 1 # miss rate for demand accesses system.cpu04.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu04.dcache.overall_miss_rate::cpu04.data 1 # miss rate for overall accesses system.cpu04.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu04.dcache.ReadReq_avg_miss_latency::cpu04.data 157250 # average ReadReq miss latency system.cpu04.dcache.ReadReq_avg_miss_latency::total 157250 # average ReadReq miss latency system.cpu04.dcache.demand_avg_miss_latency::cpu04.data 157250 # average overall miss latency system.cpu04.dcache.demand_avg_miss_latency::total 157250 # average overall miss latency system.cpu04.dcache.overall_avg_miss_latency::cpu04.data 157250 # average overall miss latency system.cpu04.dcache.overall_avg_miss_latency::total 157250 # average overall miss latency system.cpu04.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu04.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu04.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu04.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu04.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu04.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu04.dcache.ReadReq_mshr_misses::cpu04.data 2 # number of ReadReq MSHR misses system.cpu04.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu04.dcache.demand_mshr_misses::cpu04.data 2 # number of demand (read+write) MSHR misses system.cpu04.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu04.dcache.overall_mshr_misses::cpu04.data 2 # number of overall MSHR misses system.cpu04.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu04.dcache.ReadReq_mshr_miss_latency::cpu04.data 312500 # number of ReadReq MSHR miss cycles system.cpu04.dcache.ReadReq_mshr_miss_latency::total 312500 # number of ReadReq MSHR miss cycles system.cpu04.dcache.demand_mshr_miss_latency::cpu04.data 312500 # number of demand (read+write) MSHR miss cycles system.cpu04.dcache.demand_mshr_miss_latency::total 312500 # number of demand (read+write) MSHR miss cycles system.cpu04.dcache.overall_mshr_miss_latency::cpu04.data 312500 # number of overall MSHR miss cycles system.cpu04.dcache.overall_mshr_miss_latency::total 312500 # number of overall MSHR miss cycles system.cpu04.dcache.ReadReq_mshr_miss_rate::cpu04.data 1 # mshr miss rate for ReadReq accesses system.cpu04.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu04.dcache.demand_mshr_miss_rate::cpu04.data 1 # mshr miss rate for demand accesses system.cpu04.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu04.dcache.overall_mshr_miss_rate::cpu04.data 1 # mshr miss rate for overall accesses system.cpu04.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu04.dcache.ReadReq_avg_mshr_miss_latency::cpu04.data 156250 # average ReadReq mshr miss latency system.cpu04.dcache.ReadReq_avg_mshr_miss_latency::total 156250 # average ReadReq mshr miss latency system.cpu04.dcache.demand_avg_mshr_miss_latency::cpu04.data 156250 # average overall mshr miss latency system.cpu04.dcache.demand_avg_mshr_miss_latency::total 156250 # average overall mshr miss latency system.cpu04.dcache.overall_avg_mshr_miss_latency::cpu04.data 156250 # average overall mshr miss latency system.cpu04.dcache.overall_avg_mshr_miss_latency::total 156250 # average overall mshr miss latency system.cpu04.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu04.icache.tags.replacements 0 # number of replacements system.cpu04.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu04.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu04.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu04.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu04.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu04.icache.tags.occ_blocks::cpu04.inst 1.995860 # Average occupied blocks per requestor system.cpu04.icache.tags.occ_percent::cpu04.inst 0.003898 # Average percentage of cache occupancy system.cpu04.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu04.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu04.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu04.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu04.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu04.icache.tags.data_accesses 622 # Number of data accesses system.cpu04.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu04.icache.ReadReq_hits::cpu04.inst 1 # number of ReadReq hits system.cpu04.icache.ReadReq_hits::switch_cpus04.inst 152 # number of ReadReq hits system.cpu04.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu04.icache.demand_hits::cpu04.inst 1 # number of demand (read+write) hits system.cpu04.icache.demand_hits::switch_cpus04.inst 152 # number of demand (read+write) hits system.cpu04.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu04.icache.overall_hits::cpu04.inst 1 # number of overall hits system.cpu04.icache.overall_hits::switch_cpus04.inst 152 # number of overall hits system.cpu04.icache.overall_hits::total 153 # number of overall hits system.cpu04.icache.ReadReq_misses::cpu04.inst 2 # number of ReadReq misses system.cpu04.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu04.icache.demand_misses::cpu04.inst 2 # number of demand (read+write) misses system.cpu04.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu04.icache.overall_misses::cpu04.inst 2 # number of overall misses system.cpu04.icache.overall_misses::total 2 # number of overall misses system.cpu04.icache.ReadReq_miss_latency::cpu04.inst 164500 # number of ReadReq miss cycles system.cpu04.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu04.icache.demand_miss_latency::cpu04.inst 164500 # number of demand (read+write) miss cycles system.cpu04.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu04.icache.overall_miss_latency::cpu04.inst 164500 # number of overall miss cycles system.cpu04.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu04.icache.ReadReq_accesses::cpu04.inst 3 # number of ReadReq accesses(hits+misses) system.cpu04.icache.ReadReq_accesses::switch_cpus04.inst 152 # number of ReadReq accesses(hits+misses) system.cpu04.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu04.icache.demand_accesses::cpu04.inst 3 # number of demand (read+write) accesses system.cpu04.icache.demand_accesses::switch_cpus04.inst 152 # number of demand (read+write) accesses system.cpu04.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu04.icache.overall_accesses::cpu04.inst 3 # number of overall (read+write) accesses system.cpu04.icache.overall_accesses::switch_cpus04.inst 152 # number of overall (read+write) accesses system.cpu04.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu04.icache.ReadReq_miss_rate::cpu04.inst 0.666667 # miss rate for ReadReq accesses system.cpu04.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu04.icache.demand_miss_rate::cpu04.inst 0.666667 # miss rate for demand accesses system.cpu04.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu04.icache.overall_miss_rate::cpu04.inst 0.666667 # miss rate for overall accesses system.cpu04.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu04.icache.ReadReq_avg_miss_latency::cpu04.inst 82250 # average ReadReq miss latency system.cpu04.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu04.icache.demand_avg_miss_latency::cpu04.inst 82250 # average overall miss latency system.cpu04.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu04.icache.overall_avg_miss_latency::cpu04.inst 82250 # average overall miss latency system.cpu04.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu04.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu04.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu04.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu04.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu04.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu04.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu04.icache.ReadReq_mshr_misses::cpu04.inst 2 # number of ReadReq MSHR misses system.cpu04.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu04.icache.demand_mshr_misses::cpu04.inst 2 # number of demand (read+write) MSHR misses system.cpu04.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu04.icache.overall_mshr_misses::cpu04.inst 2 # number of overall MSHR misses system.cpu04.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu04.icache.ReadReq_mshr_miss_latency::cpu04.inst 162500 # number of ReadReq MSHR miss cycles system.cpu04.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu04.icache.demand_mshr_miss_latency::cpu04.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu04.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu04.icache.overall_mshr_miss_latency::cpu04.inst 162500 # number of overall MSHR miss cycles system.cpu04.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu04.icache.ReadReq_mshr_miss_rate::cpu04.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu04.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu04.icache.demand_mshr_miss_rate::cpu04.inst 0.666667 # mshr miss rate for demand accesses system.cpu04.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu04.icache.overall_mshr_miss_rate::cpu04.inst 0.666667 # mshr miss rate for overall accesses system.cpu04.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu04.icache.ReadReq_avg_mshr_miss_latency::cpu04.inst 81250 # average ReadReq mshr miss latency system.cpu04.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu04.icache.demand_avg_mshr_miss_latency::cpu04.inst 81250 # average overall mshr miss latency system.cpu04.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu04.icache.overall_avg_mshr_miss_latency::cpu04.inst 81250 # average overall mshr miss latency system.cpu04.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu05.branchPred.lookups 5 # Number of BP lookups system.cpu05.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu05.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu05.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu05.branchPred.BTBHits 0 # Number of BTB hits system.cpu05.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu05.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu05.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu05.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu05.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu05.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu05.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu05.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu05.dtb.fetch_hits 0 # ITB hits system.cpu05.dtb.fetch_misses 0 # ITB misses system.cpu05.dtb.fetch_acv 0 # ITB acv system.cpu05.dtb.fetch_accesses 0 # ITB accesses system.cpu05.dtb.read_hits 2 # DTB read hits system.cpu05.dtb.read_misses 0 # DTB read misses system.cpu05.dtb.read_acv 0 # DTB read access violations system.cpu05.dtb.read_accesses 0 # DTB read accesses system.cpu05.dtb.write_hits 0 # DTB write hits system.cpu05.dtb.write_misses 0 # DTB write misses system.cpu05.dtb.write_acv 0 # DTB write access violations system.cpu05.dtb.write_accesses 0 # DTB write accesses system.cpu05.dtb.data_hits 2 # DTB hits system.cpu05.dtb.data_misses 0 # DTB misses system.cpu05.dtb.data_acv 0 # DTB access violations system.cpu05.dtb.data_accesses 0 # DTB accesses system.cpu05.itb.fetch_hits 0 # ITB hits system.cpu05.itb.fetch_misses 1 # ITB misses system.cpu05.itb.fetch_acv 0 # ITB acv system.cpu05.itb.fetch_accesses 1 # ITB accesses system.cpu05.itb.read_hits 0 # DTB read hits system.cpu05.itb.read_misses 0 # DTB read misses system.cpu05.itb.read_acv 0 # DTB read access violations system.cpu05.itb.read_accesses 0 # DTB read accesses system.cpu05.itb.write_hits 0 # DTB write hits system.cpu05.itb.write_misses 0 # DTB write misses system.cpu05.itb.write_acv 0 # DTB write access violations system.cpu05.itb.write_accesses 0 # DTB write accesses system.cpu05.itb.data_hits 0 # DTB hits system.cpu05.itb.data_misses 0 # DTB misses system.cpu05.itb.data_acv 0 # DTB access violations system.cpu05.itb.data_accesses 0 # DTB accesses system.cpu05.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu05.numCycles 521 # number of cpu cycles simulated system.cpu05.numWorkItemsStarted 0 # number of work items this cpu started system.cpu05.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu05.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu05.fetch.Insts 10 # Number of instructions fetch has processed system.cpu05.fetch.Branches 5 # Number of branches that fetch encountered system.cpu05.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu05.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu05.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu05.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu05.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu05.fetch.CacheLines 3 # Number of cache lines fetched system.cpu05.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu05.fetch.branchRate 0.009597 # Number of branch fetches per cycle system.cpu05.fetch.rate 0.019194 # Number of inst fetches per cycle system.cpu05.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu05.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu05.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu05.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu05.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu05.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu05.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu05.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu05.rename.RunCycles 0 # Number of cycles rename is running system.cpu05.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu05.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu05.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu05.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu05.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu05.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu05.rename.serializingInsts 0 # count of serializing insts renamed system.cpu05.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu05.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu05.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu05.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu05.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu05.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu05.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu05.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu05.iq.iqInstsIssued 6 # Number of instructions issued system.cpu05.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu05.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu05.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu05.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu05.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu05.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu05.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu05.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu05.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu05.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu05.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu05.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu05.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu05.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu05.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu05.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu05.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu05.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu05.iq.FU_type_0::total 6 # Type of FU issued system.cpu05.iq.rate 0.011516 # Inst issue rate system.cpu05.iq.fu_busy_cnt 0 # FU busy when requested system.cpu05.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu05.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu05.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu05.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu05.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu05.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu05.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu05.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu05.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu05.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu05.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu05.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu05.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu05.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu05.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu05.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu05.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu05.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu05.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu05.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu05.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu05.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu05.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu05.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu05.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu05.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu05.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu05.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu05.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu05.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu05.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu05.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu05.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu05.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu05.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu05.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu05.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu05.iew.exec_swp 0 # number of swp insts executed system.cpu05.iew.exec_nop 1 # number of nop insts executed system.cpu05.iew.exec_refs 2 # number of memory reference insts executed system.cpu05.iew.exec_branches 1 # Number of branches executed system.cpu05.iew.exec_stores 0 # Number of stores executed system.cpu05.iew.exec_rate 0.011516 # Inst execution rate system.cpu05.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu05.iew.wb_count 5 # cumulative count of insts written-back system.cpu05.iew.wb_producers 1 # num instructions producing a value system.cpu05.iew.wb_consumers 1 # num instructions consuming a value system.cpu05.iew.wb_rate 0.009597 # insts written-back per cycle system.cpu05.iew.wb_fanout 1 # average fanout of values written-back system.cpu05.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu05.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu05.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu05.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu05.commit.committedInsts 1 # Number of instructions committed system.cpu05.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu05.commit.swp_count 0 # Number of s/w prefetches committed system.cpu05.commit.refs 1 # Number of memory references committed system.cpu05.commit.loads 1 # Number of loads committed system.cpu05.commit.membars 0 # Number of memory barriers committed system.cpu05.commit.branches 0 # Number of branches committed system.cpu05.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu05.commit.int_insts 1 # Number of committed integer instructions. system.cpu05.commit.function_calls 0 # Number of function calls committed. system.cpu05.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu05.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu05.commit.op_class_0::total 1 # Class of committed instruction system.cpu05.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu05.rob.rob_reads 60 # The number of ROB reads system.cpu05.rob.rob_writes 26 # The number of ROB writes system.cpu05.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu05.idleCycles 467 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu05.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu05.committedInsts 1 # Number of Instructions Simulated system.cpu05.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu05.cpi 521.000000 # CPI: Cycles Per Instruction system.cpu05.cpi_total 521.000000 # CPI: Total CPI of All Threads system.cpu05.ipc 0.001919 # IPC: Instructions Per Cycle system.cpu05.ipc_total 0.001919 # IPC: Total IPC of All Threads system.cpu05.int_regfile_reads 48 # number of integer regfile reads system.cpu05.int_regfile_writes 4 # number of integer regfile writes system.cpu05.fp_regfile_reads 32 # number of floating regfile reads system.cpu05.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu05.dcache.tags.replacements 0 # number of replacements system.cpu05.dcache.tags.tagsinuse 1.995827 # Cycle average of tags in use system.cpu05.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu05.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu05.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu05.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu05.dcache.tags.occ_blocks::cpu05.data 1.995827 # Average occupied blocks per requestor system.cpu05.dcache.tags.occ_percent::cpu05.data 0.003898 # Average percentage of cache occupancy system.cpu05.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu05.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu05.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu05.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu05.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu05.dcache.tags.data_accesses 210 # Number of data accesses system.cpu05.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu05.dcache.ReadReq_hits::switch_cpus05.data 50 # number of ReadReq hits system.cpu05.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu05.dcache.demand_hits::switch_cpus05.data 50 # number of demand (read+write) hits system.cpu05.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu05.dcache.overall_hits::switch_cpus05.data 50 # number of overall hits system.cpu05.dcache.overall_hits::total 50 # number of overall hits system.cpu05.dcache.ReadReq_misses::cpu05.data 2 # number of ReadReq misses system.cpu05.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu05.dcache.demand_misses::cpu05.data 2 # number of demand (read+write) misses system.cpu05.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu05.dcache.overall_misses::cpu05.data 2 # number of overall misses system.cpu05.dcache.overall_misses::total 2 # number of overall misses system.cpu05.dcache.ReadReq_miss_latency::cpu05.data 319500 # number of ReadReq miss cycles system.cpu05.dcache.ReadReq_miss_latency::total 319500 # number of ReadReq miss cycles system.cpu05.dcache.demand_miss_latency::cpu05.data 319500 # number of demand (read+write) miss cycles system.cpu05.dcache.demand_miss_latency::total 319500 # number of demand (read+write) miss cycles system.cpu05.dcache.overall_miss_latency::cpu05.data 319500 # number of overall miss cycles system.cpu05.dcache.overall_miss_latency::total 319500 # number of overall miss cycles system.cpu05.dcache.ReadReq_accesses::cpu05.data 2 # number of ReadReq accesses(hits+misses) system.cpu05.dcache.ReadReq_accesses::switch_cpus05.data 50 # number of ReadReq accesses(hits+misses) system.cpu05.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu05.dcache.demand_accesses::cpu05.data 2 # number of demand (read+write) accesses system.cpu05.dcache.demand_accesses::switch_cpus05.data 50 # number of demand (read+write) accesses system.cpu05.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu05.dcache.overall_accesses::cpu05.data 2 # number of overall (read+write) accesses system.cpu05.dcache.overall_accesses::switch_cpus05.data 50 # number of overall (read+write) accesses system.cpu05.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu05.dcache.ReadReq_miss_rate::cpu05.data 1 # miss rate for ReadReq accesses system.cpu05.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu05.dcache.demand_miss_rate::cpu05.data 1 # miss rate for demand accesses system.cpu05.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu05.dcache.overall_miss_rate::cpu05.data 1 # miss rate for overall accesses system.cpu05.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu05.dcache.ReadReq_avg_miss_latency::cpu05.data 159750 # average ReadReq miss latency system.cpu05.dcache.ReadReq_avg_miss_latency::total 159750 # average ReadReq miss latency system.cpu05.dcache.demand_avg_miss_latency::cpu05.data 159750 # average overall miss latency system.cpu05.dcache.demand_avg_miss_latency::total 159750 # average overall miss latency system.cpu05.dcache.overall_avg_miss_latency::cpu05.data 159750 # average overall miss latency system.cpu05.dcache.overall_avg_miss_latency::total 159750 # average overall miss latency system.cpu05.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu05.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu05.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu05.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu05.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu05.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu05.dcache.ReadReq_mshr_misses::cpu05.data 2 # number of ReadReq MSHR misses system.cpu05.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu05.dcache.demand_mshr_misses::cpu05.data 2 # number of demand (read+write) MSHR misses system.cpu05.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu05.dcache.overall_mshr_misses::cpu05.data 2 # number of overall MSHR misses system.cpu05.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu05.dcache.ReadReq_mshr_miss_latency::cpu05.data 317500 # number of ReadReq MSHR miss cycles system.cpu05.dcache.ReadReq_mshr_miss_latency::total 317500 # number of ReadReq MSHR miss cycles system.cpu05.dcache.demand_mshr_miss_latency::cpu05.data 317500 # number of demand (read+write) MSHR miss cycles system.cpu05.dcache.demand_mshr_miss_latency::total 317500 # number of demand (read+write) MSHR miss cycles system.cpu05.dcache.overall_mshr_miss_latency::cpu05.data 317500 # number of overall MSHR miss cycles system.cpu05.dcache.overall_mshr_miss_latency::total 317500 # number of overall MSHR miss cycles system.cpu05.dcache.ReadReq_mshr_miss_rate::cpu05.data 1 # mshr miss rate for ReadReq accesses system.cpu05.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu05.dcache.demand_mshr_miss_rate::cpu05.data 1 # mshr miss rate for demand accesses system.cpu05.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu05.dcache.overall_mshr_miss_rate::cpu05.data 1 # mshr miss rate for overall accesses system.cpu05.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu05.dcache.ReadReq_avg_mshr_miss_latency::cpu05.data 158750 # average ReadReq mshr miss latency system.cpu05.dcache.ReadReq_avg_mshr_miss_latency::total 158750 # average ReadReq mshr miss latency system.cpu05.dcache.demand_avg_mshr_miss_latency::cpu05.data 158750 # average overall mshr miss latency system.cpu05.dcache.demand_avg_mshr_miss_latency::total 158750 # average overall mshr miss latency system.cpu05.dcache.overall_avg_mshr_miss_latency::cpu05.data 158750 # average overall mshr miss latency system.cpu05.dcache.overall_avg_mshr_miss_latency::total 158750 # average overall mshr miss latency system.cpu05.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu05.icache.tags.replacements 0 # number of replacements system.cpu05.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu05.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu05.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu05.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu05.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu05.icache.tags.occ_blocks::cpu05.inst 1.995860 # Average occupied blocks per requestor system.cpu05.icache.tags.occ_percent::cpu05.inst 0.003898 # Average percentage of cache occupancy system.cpu05.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu05.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu05.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu05.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu05.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu05.icache.tags.data_accesses 622 # Number of data accesses system.cpu05.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu05.icache.ReadReq_hits::cpu05.inst 1 # number of ReadReq hits system.cpu05.icache.ReadReq_hits::switch_cpus05.inst 152 # number of ReadReq hits system.cpu05.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu05.icache.demand_hits::cpu05.inst 1 # number of demand (read+write) hits system.cpu05.icache.demand_hits::switch_cpus05.inst 152 # number of demand (read+write) hits system.cpu05.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu05.icache.overall_hits::cpu05.inst 1 # number of overall hits system.cpu05.icache.overall_hits::switch_cpus05.inst 152 # number of overall hits system.cpu05.icache.overall_hits::total 153 # number of overall hits system.cpu05.icache.ReadReq_misses::cpu05.inst 2 # number of ReadReq misses system.cpu05.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu05.icache.demand_misses::cpu05.inst 2 # number of demand (read+write) misses system.cpu05.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu05.icache.overall_misses::cpu05.inst 2 # number of overall misses system.cpu05.icache.overall_misses::total 2 # number of overall misses system.cpu05.icache.ReadReq_miss_latency::cpu05.inst 164500 # number of ReadReq miss cycles system.cpu05.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu05.icache.demand_miss_latency::cpu05.inst 164500 # number of demand (read+write) miss cycles system.cpu05.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu05.icache.overall_miss_latency::cpu05.inst 164500 # number of overall miss cycles system.cpu05.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu05.icache.ReadReq_accesses::cpu05.inst 3 # number of ReadReq accesses(hits+misses) system.cpu05.icache.ReadReq_accesses::switch_cpus05.inst 152 # number of ReadReq accesses(hits+misses) system.cpu05.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu05.icache.demand_accesses::cpu05.inst 3 # number of demand (read+write) accesses system.cpu05.icache.demand_accesses::switch_cpus05.inst 152 # number of demand (read+write) accesses system.cpu05.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu05.icache.overall_accesses::cpu05.inst 3 # number of overall (read+write) accesses system.cpu05.icache.overall_accesses::switch_cpus05.inst 152 # number of overall (read+write) accesses system.cpu05.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu05.icache.ReadReq_miss_rate::cpu05.inst 0.666667 # miss rate for ReadReq accesses system.cpu05.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu05.icache.demand_miss_rate::cpu05.inst 0.666667 # miss rate for demand accesses system.cpu05.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu05.icache.overall_miss_rate::cpu05.inst 0.666667 # miss rate for overall accesses system.cpu05.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu05.icache.ReadReq_avg_miss_latency::cpu05.inst 82250 # average ReadReq miss latency system.cpu05.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu05.icache.demand_avg_miss_latency::cpu05.inst 82250 # average overall miss latency system.cpu05.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu05.icache.overall_avg_miss_latency::cpu05.inst 82250 # average overall miss latency system.cpu05.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu05.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu05.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu05.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu05.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu05.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu05.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu05.icache.ReadReq_mshr_misses::cpu05.inst 2 # number of ReadReq MSHR misses system.cpu05.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu05.icache.demand_mshr_misses::cpu05.inst 2 # number of demand (read+write) MSHR misses system.cpu05.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu05.icache.overall_mshr_misses::cpu05.inst 2 # number of overall MSHR misses system.cpu05.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu05.icache.ReadReq_mshr_miss_latency::cpu05.inst 162500 # number of ReadReq MSHR miss cycles system.cpu05.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu05.icache.demand_mshr_miss_latency::cpu05.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu05.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu05.icache.overall_mshr_miss_latency::cpu05.inst 162500 # number of overall MSHR miss cycles system.cpu05.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu05.icache.ReadReq_mshr_miss_rate::cpu05.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu05.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu05.icache.demand_mshr_miss_rate::cpu05.inst 0.666667 # mshr miss rate for demand accesses system.cpu05.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu05.icache.overall_mshr_miss_rate::cpu05.inst 0.666667 # mshr miss rate for overall accesses system.cpu05.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu05.icache.ReadReq_avg_mshr_miss_latency::cpu05.inst 81250 # average ReadReq mshr miss latency system.cpu05.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu05.icache.demand_avg_mshr_miss_latency::cpu05.inst 81250 # average overall mshr miss latency system.cpu05.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu05.icache.overall_avg_mshr_miss_latency::cpu05.inst 81250 # average overall mshr miss latency system.cpu05.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu06.branchPred.lookups 5 # Number of BP lookups system.cpu06.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu06.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu06.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu06.branchPred.BTBHits 0 # Number of BTB hits system.cpu06.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu06.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu06.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu06.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu06.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu06.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu06.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu06.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu06.dtb.fetch_hits 0 # ITB hits system.cpu06.dtb.fetch_misses 0 # ITB misses system.cpu06.dtb.fetch_acv 0 # ITB acv system.cpu06.dtb.fetch_accesses 0 # ITB accesses system.cpu06.dtb.read_hits 2 # DTB read hits system.cpu06.dtb.read_misses 0 # DTB read misses system.cpu06.dtb.read_acv 0 # DTB read access violations system.cpu06.dtb.read_accesses 0 # DTB read accesses system.cpu06.dtb.write_hits 0 # DTB write hits system.cpu06.dtb.write_misses 0 # DTB write misses system.cpu06.dtb.write_acv 0 # DTB write access violations system.cpu06.dtb.write_accesses 0 # DTB write accesses system.cpu06.dtb.data_hits 2 # DTB hits system.cpu06.dtb.data_misses 0 # DTB misses system.cpu06.dtb.data_acv 0 # DTB access violations system.cpu06.dtb.data_accesses 0 # DTB accesses system.cpu06.itb.fetch_hits 0 # ITB hits system.cpu06.itb.fetch_misses 1 # ITB misses system.cpu06.itb.fetch_acv 0 # ITB acv system.cpu06.itb.fetch_accesses 1 # ITB accesses system.cpu06.itb.read_hits 0 # DTB read hits system.cpu06.itb.read_misses 0 # DTB read misses system.cpu06.itb.read_acv 0 # DTB read access violations system.cpu06.itb.read_accesses 0 # DTB read accesses system.cpu06.itb.write_hits 0 # DTB write hits system.cpu06.itb.write_misses 0 # DTB write misses system.cpu06.itb.write_acv 0 # DTB write access violations system.cpu06.itb.write_accesses 0 # DTB write accesses system.cpu06.itb.data_hits 0 # DTB hits system.cpu06.itb.data_misses 0 # DTB misses system.cpu06.itb.data_acv 0 # DTB access violations system.cpu06.itb.data_accesses 0 # DTB accesses system.cpu06.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu06.numCycles 531 # number of cpu cycles simulated system.cpu06.numWorkItemsStarted 0 # number of work items this cpu started system.cpu06.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu06.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu06.fetch.Insts 10 # Number of instructions fetch has processed system.cpu06.fetch.Branches 5 # Number of branches that fetch encountered system.cpu06.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu06.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu06.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu06.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu06.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu06.fetch.CacheLines 3 # Number of cache lines fetched system.cpu06.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu06.fetch.branchRate 0.009416 # Number of branch fetches per cycle system.cpu06.fetch.rate 0.018832 # Number of inst fetches per cycle system.cpu06.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu06.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu06.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu06.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu06.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu06.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu06.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu06.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu06.rename.RunCycles 0 # Number of cycles rename is running system.cpu06.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu06.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu06.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu06.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu06.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu06.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu06.rename.serializingInsts 0 # count of serializing insts renamed system.cpu06.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu06.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu06.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu06.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu06.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu06.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu06.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu06.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu06.iq.iqInstsIssued 6 # Number of instructions issued system.cpu06.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu06.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu06.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu06.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu06.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu06.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu06.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu06.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu06.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu06.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu06.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu06.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu06.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu06.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu06.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu06.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu06.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu06.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu06.iq.FU_type_0::total 6 # Type of FU issued system.cpu06.iq.rate 0.011299 # Inst issue rate system.cpu06.iq.fu_busy_cnt 0 # FU busy when requested system.cpu06.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu06.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu06.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu06.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu06.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu06.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu06.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu06.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu06.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu06.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu06.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu06.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu06.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu06.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu06.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu06.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu06.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu06.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu06.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu06.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu06.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu06.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu06.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu06.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu06.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu06.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu06.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu06.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu06.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu06.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu06.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu06.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu06.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu06.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu06.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu06.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu06.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu06.iew.exec_swp 0 # number of swp insts executed system.cpu06.iew.exec_nop 1 # number of nop insts executed system.cpu06.iew.exec_refs 2 # number of memory reference insts executed system.cpu06.iew.exec_branches 1 # Number of branches executed system.cpu06.iew.exec_stores 0 # Number of stores executed system.cpu06.iew.exec_rate 0.011299 # Inst execution rate system.cpu06.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu06.iew.wb_count 5 # cumulative count of insts written-back system.cpu06.iew.wb_producers 1 # num instructions producing a value system.cpu06.iew.wb_consumers 1 # num instructions consuming a value system.cpu06.iew.wb_rate 0.009416 # insts written-back per cycle system.cpu06.iew.wb_fanout 1 # average fanout of values written-back system.cpu06.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu06.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu06.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu06.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu06.commit.committedInsts 1 # Number of instructions committed system.cpu06.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu06.commit.swp_count 0 # Number of s/w prefetches committed system.cpu06.commit.refs 1 # Number of memory references committed system.cpu06.commit.loads 1 # Number of loads committed system.cpu06.commit.membars 0 # Number of memory barriers committed system.cpu06.commit.branches 0 # Number of branches committed system.cpu06.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu06.commit.int_insts 1 # Number of committed integer instructions. system.cpu06.commit.function_calls 0 # Number of function calls committed. system.cpu06.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu06.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu06.commit.op_class_0::total 1 # Class of committed instruction system.cpu06.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu06.rob.rob_reads 60 # The number of ROB reads system.cpu06.rob.rob_writes 26 # The number of ROB writes system.cpu06.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu06.idleCycles 477 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu06.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu06.committedInsts 1 # Number of Instructions Simulated system.cpu06.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu06.cpi 531.000000 # CPI: Cycles Per Instruction system.cpu06.cpi_total 531.000000 # CPI: Total CPI of All Threads system.cpu06.ipc 0.001883 # IPC: Instructions Per Cycle system.cpu06.ipc_total 0.001883 # IPC: Total IPC of All Threads system.cpu06.int_regfile_reads 48 # number of integer regfile reads system.cpu06.int_regfile_writes 4 # number of integer regfile writes system.cpu06.fp_regfile_reads 32 # number of floating regfile reads system.cpu06.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu06.dcache.tags.replacements 0 # number of replacements system.cpu06.dcache.tags.tagsinuse 1.995827 # Cycle average of tags in use system.cpu06.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu06.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu06.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu06.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu06.dcache.tags.occ_blocks::cpu06.data 1.995827 # Average occupied blocks per requestor system.cpu06.dcache.tags.occ_percent::cpu06.data 0.003898 # Average percentage of cache occupancy system.cpu06.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu06.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu06.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu06.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu06.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu06.dcache.tags.data_accesses 210 # Number of data accesses system.cpu06.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu06.dcache.ReadReq_hits::switch_cpus06.data 50 # number of ReadReq hits system.cpu06.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu06.dcache.demand_hits::switch_cpus06.data 50 # number of demand (read+write) hits system.cpu06.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu06.dcache.overall_hits::switch_cpus06.data 50 # number of overall hits system.cpu06.dcache.overall_hits::total 50 # number of overall hits system.cpu06.dcache.ReadReq_misses::cpu06.data 2 # number of ReadReq misses system.cpu06.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu06.dcache.demand_misses::cpu06.data 2 # number of demand (read+write) misses system.cpu06.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu06.dcache.overall_misses::cpu06.data 2 # number of overall misses system.cpu06.dcache.overall_misses::total 2 # number of overall misses system.cpu06.dcache.ReadReq_miss_latency::cpu06.data 324500 # number of ReadReq miss cycles system.cpu06.dcache.ReadReq_miss_latency::total 324500 # number of ReadReq miss cycles system.cpu06.dcache.demand_miss_latency::cpu06.data 324500 # number of demand (read+write) miss cycles system.cpu06.dcache.demand_miss_latency::total 324500 # number of demand (read+write) miss cycles system.cpu06.dcache.overall_miss_latency::cpu06.data 324500 # number of overall miss cycles system.cpu06.dcache.overall_miss_latency::total 324500 # number of overall miss cycles system.cpu06.dcache.ReadReq_accesses::cpu06.data 2 # number of ReadReq accesses(hits+misses) system.cpu06.dcache.ReadReq_accesses::switch_cpus06.data 50 # number of ReadReq accesses(hits+misses) system.cpu06.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu06.dcache.demand_accesses::cpu06.data 2 # number of demand (read+write) accesses system.cpu06.dcache.demand_accesses::switch_cpus06.data 50 # number of demand (read+write) accesses system.cpu06.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu06.dcache.overall_accesses::cpu06.data 2 # number of overall (read+write) accesses system.cpu06.dcache.overall_accesses::switch_cpus06.data 50 # number of overall (read+write) accesses system.cpu06.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu06.dcache.ReadReq_miss_rate::cpu06.data 1 # miss rate for ReadReq accesses system.cpu06.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu06.dcache.demand_miss_rate::cpu06.data 1 # miss rate for demand accesses system.cpu06.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu06.dcache.overall_miss_rate::cpu06.data 1 # miss rate for overall accesses system.cpu06.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu06.dcache.ReadReq_avg_miss_latency::cpu06.data 162250 # average ReadReq miss latency system.cpu06.dcache.ReadReq_avg_miss_latency::total 162250 # average ReadReq miss latency system.cpu06.dcache.demand_avg_miss_latency::cpu06.data 162250 # average overall miss latency system.cpu06.dcache.demand_avg_miss_latency::total 162250 # average overall miss latency system.cpu06.dcache.overall_avg_miss_latency::cpu06.data 162250 # average overall miss latency system.cpu06.dcache.overall_avg_miss_latency::total 162250 # average overall miss latency system.cpu06.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu06.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu06.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu06.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu06.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu06.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu06.dcache.ReadReq_mshr_misses::cpu06.data 2 # number of ReadReq MSHR misses system.cpu06.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu06.dcache.demand_mshr_misses::cpu06.data 2 # number of demand (read+write) MSHR misses system.cpu06.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu06.dcache.overall_mshr_misses::cpu06.data 2 # number of overall MSHR misses system.cpu06.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu06.dcache.ReadReq_mshr_miss_latency::cpu06.data 322500 # number of ReadReq MSHR miss cycles system.cpu06.dcache.ReadReq_mshr_miss_latency::total 322500 # number of ReadReq MSHR miss cycles system.cpu06.dcache.demand_mshr_miss_latency::cpu06.data 322500 # number of demand (read+write) MSHR miss cycles system.cpu06.dcache.demand_mshr_miss_latency::total 322500 # number of demand (read+write) MSHR miss cycles system.cpu06.dcache.overall_mshr_miss_latency::cpu06.data 322500 # number of overall MSHR miss cycles system.cpu06.dcache.overall_mshr_miss_latency::total 322500 # number of overall MSHR miss cycles system.cpu06.dcache.ReadReq_mshr_miss_rate::cpu06.data 1 # mshr miss rate for ReadReq accesses system.cpu06.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu06.dcache.demand_mshr_miss_rate::cpu06.data 1 # mshr miss rate for demand accesses system.cpu06.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu06.dcache.overall_mshr_miss_rate::cpu06.data 1 # mshr miss rate for overall accesses system.cpu06.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu06.dcache.ReadReq_avg_mshr_miss_latency::cpu06.data 161250 # average ReadReq mshr miss latency system.cpu06.dcache.ReadReq_avg_mshr_miss_latency::total 161250 # average ReadReq mshr miss latency system.cpu06.dcache.demand_avg_mshr_miss_latency::cpu06.data 161250 # average overall mshr miss latency system.cpu06.dcache.demand_avg_mshr_miss_latency::total 161250 # average overall mshr miss latency system.cpu06.dcache.overall_avg_mshr_miss_latency::cpu06.data 161250 # average overall mshr miss latency system.cpu06.dcache.overall_avg_mshr_miss_latency::total 161250 # average overall mshr miss latency system.cpu06.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu06.icache.tags.replacements 0 # number of replacements system.cpu06.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu06.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu06.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu06.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu06.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu06.icache.tags.occ_blocks::cpu06.inst 1.995860 # Average occupied blocks per requestor system.cpu06.icache.tags.occ_percent::cpu06.inst 0.003898 # Average percentage of cache occupancy system.cpu06.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu06.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu06.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu06.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu06.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu06.icache.tags.data_accesses 622 # Number of data accesses system.cpu06.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu06.icache.ReadReq_hits::cpu06.inst 1 # number of ReadReq hits system.cpu06.icache.ReadReq_hits::switch_cpus06.inst 152 # number of ReadReq hits system.cpu06.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu06.icache.demand_hits::cpu06.inst 1 # number of demand (read+write) hits system.cpu06.icache.demand_hits::switch_cpus06.inst 152 # number of demand (read+write) hits system.cpu06.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu06.icache.overall_hits::cpu06.inst 1 # number of overall hits system.cpu06.icache.overall_hits::switch_cpus06.inst 152 # number of overall hits system.cpu06.icache.overall_hits::total 153 # number of overall hits system.cpu06.icache.ReadReq_misses::cpu06.inst 2 # number of ReadReq misses system.cpu06.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu06.icache.demand_misses::cpu06.inst 2 # number of demand (read+write) misses system.cpu06.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu06.icache.overall_misses::cpu06.inst 2 # number of overall misses system.cpu06.icache.overall_misses::total 2 # number of overall misses system.cpu06.icache.ReadReq_miss_latency::cpu06.inst 164500 # number of ReadReq miss cycles system.cpu06.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu06.icache.demand_miss_latency::cpu06.inst 164500 # number of demand (read+write) miss cycles system.cpu06.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu06.icache.overall_miss_latency::cpu06.inst 164500 # number of overall miss cycles system.cpu06.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu06.icache.ReadReq_accesses::cpu06.inst 3 # number of ReadReq accesses(hits+misses) system.cpu06.icache.ReadReq_accesses::switch_cpus06.inst 152 # number of ReadReq accesses(hits+misses) system.cpu06.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu06.icache.demand_accesses::cpu06.inst 3 # number of demand (read+write) accesses system.cpu06.icache.demand_accesses::switch_cpus06.inst 152 # number of demand (read+write) accesses system.cpu06.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu06.icache.overall_accesses::cpu06.inst 3 # number of overall (read+write) accesses system.cpu06.icache.overall_accesses::switch_cpus06.inst 152 # number of overall (read+write) accesses system.cpu06.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu06.icache.ReadReq_miss_rate::cpu06.inst 0.666667 # miss rate for ReadReq accesses system.cpu06.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu06.icache.demand_miss_rate::cpu06.inst 0.666667 # miss rate for demand accesses system.cpu06.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu06.icache.overall_miss_rate::cpu06.inst 0.666667 # miss rate for overall accesses system.cpu06.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu06.icache.ReadReq_avg_miss_latency::cpu06.inst 82250 # average ReadReq miss latency system.cpu06.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu06.icache.demand_avg_miss_latency::cpu06.inst 82250 # average overall miss latency system.cpu06.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu06.icache.overall_avg_miss_latency::cpu06.inst 82250 # average overall miss latency system.cpu06.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu06.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu06.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu06.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu06.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu06.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu06.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu06.icache.ReadReq_mshr_misses::cpu06.inst 2 # number of ReadReq MSHR misses system.cpu06.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu06.icache.demand_mshr_misses::cpu06.inst 2 # number of demand (read+write) MSHR misses system.cpu06.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu06.icache.overall_mshr_misses::cpu06.inst 2 # number of overall MSHR misses system.cpu06.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu06.icache.ReadReq_mshr_miss_latency::cpu06.inst 162500 # number of ReadReq MSHR miss cycles system.cpu06.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu06.icache.demand_mshr_miss_latency::cpu06.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu06.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu06.icache.overall_mshr_miss_latency::cpu06.inst 162500 # number of overall MSHR miss cycles system.cpu06.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu06.icache.ReadReq_mshr_miss_rate::cpu06.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu06.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu06.icache.demand_mshr_miss_rate::cpu06.inst 0.666667 # mshr miss rate for demand accesses system.cpu06.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu06.icache.overall_mshr_miss_rate::cpu06.inst 0.666667 # mshr miss rate for overall accesses system.cpu06.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu06.icache.ReadReq_avg_mshr_miss_latency::cpu06.inst 81250 # average ReadReq mshr miss latency system.cpu06.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu06.icache.demand_avg_mshr_miss_latency::cpu06.inst 81250 # average overall mshr miss latency system.cpu06.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu06.icache.overall_avg_mshr_miss_latency::cpu06.inst 81250 # average overall mshr miss latency system.cpu06.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu07.branchPred.lookups 5 # Number of BP lookups system.cpu07.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu07.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu07.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu07.branchPred.BTBHits 0 # Number of BTB hits system.cpu07.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu07.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu07.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu07.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu07.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu07.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu07.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu07.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu07.dtb.fetch_hits 0 # ITB hits system.cpu07.dtb.fetch_misses 0 # ITB misses system.cpu07.dtb.fetch_acv 0 # ITB acv system.cpu07.dtb.fetch_accesses 0 # ITB accesses system.cpu07.dtb.read_hits 2 # DTB read hits system.cpu07.dtb.read_misses 0 # DTB read misses system.cpu07.dtb.read_acv 0 # DTB read access violations system.cpu07.dtb.read_accesses 0 # DTB read accesses system.cpu07.dtb.write_hits 0 # DTB write hits system.cpu07.dtb.write_misses 0 # DTB write misses system.cpu07.dtb.write_acv 0 # DTB write access violations system.cpu07.dtb.write_accesses 0 # DTB write accesses system.cpu07.dtb.data_hits 2 # DTB hits system.cpu07.dtb.data_misses 0 # DTB misses system.cpu07.dtb.data_acv 0 # DTB access violations system.cpu07.dtb.data_accesses 0 # DTB accesses system.cpu07.itb.fetch_hits 0 # ITB hits system.cpu07.itb.fetch_misses 1 # ITB misses system.cpu07.itb.fetch_acv 0 # ITB acv system.cpu07.itb.fetch_accesses 1 # ITB accesses system.cpu07.itb.read_hits 0 # DTB read hits system.cpu07.itb.read_misses 0 # DTB read misses system.cpu07.itb.read_acv 0 # DTB read access violations system.cpu07.itb.read_accesses 0 # DTB read accesses system.cpu07.itb.write_hits 0 # DTB write hits system.cpu07.itb.write_misses 0 # DTB write misses system.cpu07.itb.write_acv 0 # DTB write access violations system.cpu07.itb.write_accesses 0 # DTB write accesses system.cpu07.itb.data_hits 0 # DTB hits system.cpu07.itb.data_misses 0 # DTB misses system.cpu07.itb.data_acv 0 # DTB access violations system.cpu07.itb.data_accesses 0 # DTB accesses system.cpu07.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu07.numCycles 541 # number of cpu cycles simulated system.cpu07.numWorkItemsStarted 0 # number of work items this cpu started system.cpu07.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu07.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu07.fetch.Insts 10 # Number of instructions fetch has processed system.cpu07.fetch.Branches 5 # Number of branches that fetch encountered system.cpu07.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu07.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu07.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu07.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu07.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu07.fetch.CacheLines 3 # Number of cache lines fetched system.cpu07.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu07.fetch.branchRate 0.009242 # Number of branch fetches per cycle system.cpu07.fetch.rate 0.018484 # Number of inst fetches per cycle system.cpu07.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu07.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu07.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu07.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu07.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu07.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu07.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu07.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu07.rename.RunCycles 0 # Number of cycles rename is running system.cpu07.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu07.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu07.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu07.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu07.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu07.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu07.rename.serializingInsts 0 # count of serializing insts renamed system.cpu07.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu07.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu07.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu07.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu07.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu07.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu07.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu07.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu07.iq.iqInstsIssued 6 # Number of instructions issued system.cpu07.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu07.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu07.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu07.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu07.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu07.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu07.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu07.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu07.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu07.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu07.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu07.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu07.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu07.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu07.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu07.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu07.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu07.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu07.iq.FU_type_0::total 6 # Type of FU issued system.cpu07.iq.rate 0.011091 # Inst issue rate system.cpu07.iq.fu_busy_cnt 0 # FU busy when requested system.cpu07.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu07.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu07.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu07.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu07.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu07.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu07.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu07.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu07.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu07.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu07.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu07.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu07.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu07.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu07.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu07.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu07.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu07.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu07.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu07.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu07.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu07.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu07.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu07.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu07.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu07.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu07.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu07.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu07.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu07.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu07.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu07.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu07.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu07.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu07.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu07.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu07.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu07.iew.exec_swp 0 # number of swp insts executed system.cpu07.iew.exec_nop 1 # number of nop insts executed system.cpu07.iew.exec_refs 2 # number of memory reference insts executed system.cpu07.iew.exec_branches 1 # Number of branches executed system.cpu07.iew.exec_stores 0 # Number of stores executed system.cpu07.iew.exec_rate 0.011091 # Inst execution rate system.cpu07.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu07.iew.wb_count 5 # cumulative count of insts written-back system.cpu07.iew.wb_producers 1 # num instructions producing a value system.cpu07.iew.wb_consumers 1 # num instructions consuming a value system.cpu07.iew.wb_rate 0.009242 # insts written-back per cycle system.cpu07.iew.wb_fanout 1 # average fanout of values written-back system.cpu07.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu07.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu07.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu07.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu07.commit.committedInsts 1 # Number of instructions committed system.cpu07.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu07.commit.swp_count 0 # Number of s/w prefetches committed system.cpu07.commit.refs 1 # Number of memory references committed system.cpu07.commit.loads 1 # Number of loads committed system.cpu07.commit.membars 0 # Number of memory barriers committed system.cpu07.commit.branches 0 # Number of branches committed system.cpu07.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu07.commit.int_insts 1 # Number of committed integer instructions. system.cpu07.commit.function_calls 0 # Number of function calls committed. system.cpu07.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu07.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu07.commit.op_class_0::total 1 # Class of committed instruction system.cpu07.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu07.rob.rob_reads 60 # The number of ROB reads system.cpu07.rob.rob_writes 26 # The number of ROB writes system.cpu07.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu07.idleCycles 487 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu07.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu07.committedInsts 1 # Number of Instructions Simulated system.cpu07.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu07.cpi 541.000000 # CPI: Cycles Per Instruction system.cpu07.cpi_total 541.000000 # CPI: Total CPI of All Threads system.cpu07.ipc 0.001848 # IPC: Instructions Per Cycle system.cpu07.ipc_total 0.001848 # IPC: Total IPC of All Threads system.cpu07.int_regfile_reads 48 # number of integer regfile reads system.cpu07.int_regfile_writes 4 # number of integer regfile writes system.cpu07.fp_regfile_reads 32 # number of floating regfile reads system.cpu07.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu07.dcache.tags.replacements 0 # number of replacements system.cpu07.dcache.tags.tagsinuse 1.995826 # Cycle average of tags in use system.cpu07.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu07.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu07.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu07.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu07.dcache.tags.occ_blocks::cpu07.data 1.995826 # Average occupied blocks per requestor system.cpu07.dcache.tags.occ_percent::cpu07.data 0.003898 # Average percentage of cache occupancy system.cpu07.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu07.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu07.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu07.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu07.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu07.dcache.tags.data_accesses 210 # Number of data accesses system.cpu07.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu07.dcache.ReadReq_hits::switch_cpus07.data 50 # number of ReadReq hits system.cpu07.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu07.dcache.demand_hits::switch_cpus07.data 50 # number of demand (read+write) hits system.cpu07.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu07.dcache.overall_hits::switch_cpus07.data 50 # number of overall hits system.cpu07.dcache.overall_hits::total 50 # number of overall hits system.cpu07.dcache.ReadReq_misses::cpu07.data 2 # number of ReadReq misses system.cpu07.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu07.dcache.demand_misses::cpu07.data 2 # number of demand (read+write) misses system.cpu07.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu07.dcache.overall_misses::cpu07.data 2 # number of overall misses system.cpu07.dcache.overall_misses::total 2 # number of overall misses system.cpu07.dcache.ReadReq_miss_latency::cpu07.data 329500 # number of ReadReq miss cycles system.cpu07.dcache.ReadReq_miss_latency::total 329500 # number of ReadReq miss cycles system.cpu07.dcache.demand_miss_latency::cpu07.data 329500 # number of demand (read+write) miss cycles system.cpu07.dcache.demand_miss_latency::total 329500 # number of demand (read+write) miss cycles system.cpu07.dcache.overall_miss_latency::cpu07.data 329500 # number of overall miss cycles system.cpu07.dcache.overall_miss_latency::total 329500 # number of overall miss cycles system.cpu07.dcache.ReadReq_accesses::cpu07.data 2 # number of ReadReq accesses(hits+misses) system.cpu07.dcache.ReadReq_accesses::switch_cpus07.data 50 # number of ReadReq accesses(hits+misses) system.cpu07.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu07.dcache.demand_accesses::cpu07.data 2 # number of demand (read+write) accesses system.cpu07.dcache.demand_accesses::switch_cpus07.data 50 # number of demand (read+write) accesses system.cpu07.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu07.dcache.overall_accesses::cpu07.data 2 # number of overall (read+write) accesses system.cpu07.dcache.overall_accesses::switch_cpus07.data 50 # number of overall (read+write) accesses system.cpu07.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu07.dcache.ReadReq_miss_rate::cpu07.data 1 # miss rate for ReadReq accesses system.cpu07.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu07.dcache.demand_miss_rate::cpu07.data 1 # miss rate for demand accesses system.cpu07.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu07.dcache.overall_miss_rate::cpu07.data 1 # miss rate for overall accesses system.cpu07.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu07.dcache.ReadReq_avg_miss_latency::cpu07.data 164750 # average ReadReq miss latency system.cpu07.dcache.ReadReq_avg_miss_latency::total 164750 # average ReadReq miss latency system.cpu07.dcache.demand_avg_miss_latency::cpu07.data 164750 # average overall miss latency system.cpu07.dcache.demand_avg_miss_latency::total 164750 # average overall miss latency system.cpu07.dcache.overall_avg_miss_latency::cpu07.data 164750 # average overall miss latency system.cpu07.dcache.overall_avg_miss_latency::total 164750 # average overall miss latency system.cpu07.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu07.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu07.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu07.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu07.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu07.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu07.dcache.ReadReq_mshr_misses::cpu07.data 2 # number of ReadReq MSHR misses system.cpu07.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu07.dcache.demand_mshr_misses::cpu07.data 2 # number of demand (read+write) MSHR misses system.cpu07.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu07.dcache.overall_mshr_misses::cpu07.data 2 # number of overall MSHR misses system.cpu07.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu07.dcache.ReadReq_mshr_miss_latency::cpu07.data 327500 # number of ReadReq MSHR miss cycles system.cpu07.dcache.ReadReq_mshr_miss_latency::total 327500 # number of ReadReq MSHR miss cycles system.cpu07.dcache.demand_mshr_miss_latency::cpu07.data 327500 # number of demand (read+write) MSHR miss cycles system.cpu07.dcache.demand_mshr_miss_latency::total 327500 # number of demand (read+write) MSHR miss cycles system.cpu07.dcache.overall_mshr_miss_latency::cpu07.data 327500 # number of overall MSHR miss cycles system.cpu07.dcache.overall_mshr_miss_latency::total 327500 # number of overall MSHR miss cycles system.cpu07.dcache.ReadReq_mshr_miss_rate::cpu07.data 1 # mshr miss rate for ReadReq accesses system.cpu07.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu07.dcache.demand_mshr_miss_rate::cpu07.data 1 # mshr miss rate for demand accesses system.cpu07.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu07.dcache.overall_mshr_miss_rate::cpu07.data 1 # mshr miss rate for overall accesses system.cpu07.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu07.dcache.ReadReq_avg_mshr_miss_latency::cpu07.data 163750 # average ReadReq mshr miss latency system.cpu07.dcache.ReadReq_avg_mshr_miss_latency::total 163750 # average ReadReq mshr miss latency system.cpu07.dcache.demand_avg_mshr_miss_latency::cpu07.data 163750 # average overall mshr miss latency system.cpu07.dcache.demand_avg_mshr_miss_latency::total 163750 # average overall mshr miss latency system.cpu07.dcache.overall_avg_mshr_miss_latency::cpu07.data 163750 # average overall mshr miss latency system.cpu07.dcache.overall_avg_mshr_miss_latency::total 163750 # average overall mshr miss latency system.cpu07.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu07.icache.tags.replacements 0 # number of replacements system.cpu07.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu07.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu07.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu07.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu07.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu07.icache.tags.occ_blocks::cpu07.inst 1.995860 # Average occupied blocks per requestor system.cpu07.icache.tags.occ_percent::cpu07.inst 0.003898 # Average percentage of cache occupancy system.cpu07.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu07.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu07.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu07.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu07.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu07.icache.tags.data_accesses 622 # Number of data accesses system.cpu07.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu07.icache.ReadReq_hits::cpu07.inst 1 # number of ReadReq hits system.cpu07.icache.ReadReq_hits::switch_cpus07.inst 152 # number of ReadReq hits system.cpu07.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu07.icache.demand_hits::cpu07.inst 1 # number of demand (read+write) hits system.cpu07.icache.demand_hits::switch_cpus07.inst 152 # number of demand (read+write) hits system.cpu07.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu07.icache.overall_hits::cpu07.inst 1 # number of overall hits system.cpu07.icache.overall_hits::switch_cpus07.inst 152 # number of overall hits system.cpu07.icache.overall_hits::total 153 # number of overall hits system.cpu07.icache.ReadReq_misses::cpu07.inst 2 # number of ReadReq misses system.cpu07.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu07.icache.demand_misses::cpu07.inst 2 # number of demand (read+write) misses system.cpu07.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu07.icache.overall_misses::cpu07.inst 2 # number of overall misses system.cpu07.icache.overall_misses::total 2 # number of overall misses system.cpu07.icache.ReadReq_miss_latency::cpu07.inst 164500 # number of ReadReq miss cycles system.cpu07.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu07.icache.demand_miss_latency::cpu07.inst 164500 # number of demand (read+write) miss cycles system.cpu07.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu07.icache.overall_miss_latency::cpu07.inst 164500 # number of overall miss cycles system.cpu07.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu07.icache.ReadReq_accesses::cpu07.inst 3 # number of ReadReq accesses(hits+misses) system.cpu07.icache.ReadReq_accesses::switch_cpus07.inst 152 # number of ReadReq accesses(hits+misses) system.cpu07.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu07.icache.demand_accesses::cpu07.inst 3 # number of demand (read+write) accesses system.cpu07.icache.demand_accesses::switch_cpus07.inst 152 # number of demand (read+write) accesses system.cpu07.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu07.icache.overall_accesses::cpu07.inst 3 # number of overall (read+write) accesses system.cpu07.icache.overall_accesses::switch_cpus07.inst 152 # number of overall (read+write) accesses system.cpu07.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu07.icache.ReadReq_miss_rate::cpu07.inst 0.666667 # miss rate for ReadReq accesses system.cpu07.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu07.icache.demand_miss_rate::cpu07.inst 0.666667 # miss rate for demand accesses system.cpu07.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu07.icache.overall_miss_rate::cpu07.inst 0.666667 # miss rate for overall accesses system.cpu07.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu07.icache.ReadReq_avg_miss_latency::cpu07.inst 82250 # average ReadReq miss latency system.cpu07.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu07.icache.demand_avg_miss_latency::cpu07.inst 82250 # average overall miss latency system.cpu07.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu07.icache.overall_avg_miss_latency::cpu07.inst 82250 # average overall miss latency system.cpu07.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu07.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu07.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu07.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu07.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu07.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu07.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu07.icache.ReadReq_mshr_misses::cpu07.inst 2 # number of ReadReq MSHR misses system.cpu07.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu07.icache.demand_mshr_misses::cpu07.inst 2 # number of demand (read+write) MSHR misses system.cpu07.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu07.icache.overall_mshr_misses::cpu07.inst 2 # number of overall MSHR misses system.cpu07.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu07.icache.ReadReq_mshr_miss_latency::cpu07.inst 162500 # number of ReadReq MSHR miss cycles system.cpu07.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu07.icache.demand_mshr_miss_latency::cpu07.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu07.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu07.icache.overall_mshr_miss_latency::cpu07.inst 162500 # number of overall MSHR miss cycles system.cpu07.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu07.icache.ReadReq_mshr_miss_rate::cpu07.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu07.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu07.icache.demand_mshr_miss_rate::cpu07.inst 0.666667 # mshr miss rate for demand accesses system.cpu07.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu07.icache.overall_mshr_miss_rate::cpu07.inst 0.666667 # mshr miss rate for overall accesses system.cpu07.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu07.icache.ReadReq_avg_mshr_miss_latency::cpu07.inst 81250 # average ReadReq mshr miss latency system.cpu07.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu07.icache.demand_avg_mshr_miss_latency::cpu07.inst 81250 # average overall mshr miss latency system.cpu07.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu07.icache.overall_avg_mshr_miss_latency::cpu07.inst 81250 # average overall mshr miss latency system.cpu07.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu08.branchPred.lookups 5 # Number of BP lookups system.cpu08.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu08.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu08.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu08.branchPred.BTBHits 0 # Number of BTB hits system.cpu08.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu08.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu08.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu08.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu08.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu08.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu08.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu08.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu08.dtb.fetch_hits 0 # ITB hits system.cpu08.dtb.fetch_misses 0 # ITB misses system.cpu08.dtb.fetch_acv 0 # ITB acv system.cpu08.dtb.fetch_accesses 0 # ITB accesses system.cpu08.dtb.read_hits 2 # DTB read hits system.cpu08.dtb.read_misses 0 # DTB read misses system.cpu08.dtb.read_acv 0 # DTB read access violations system.cpu08.dtb.read_accesses 0 # DTB read accesses system.cpu08.dtb.write_hits 0 # DTB write hits system.cpu08.dtb.write_misses 0 # DTB write misses system.cpu08.dtb.write_acv 0 # DTB write access violations system.cpu08.dtb.write_accesses 0 # DTB write accesses system.cpu08.dtb.data_hits 2 # DTB hits system.cpu08.dtb.data_misses 0 # DTB misses system.cpu08.dtb.data_acv 0 # DTB access violations system.cpu08.dtb.data_accesses 0 # DTB accesses system.cpu08.itb.fetch_hits 0 # ITB hits system.cpu08.itb.fetch_misses 1 # ITB misses system.cpu08.itb.fetch_acv 0 # ITB acv system.cpu08.itb.fetch_accesses 1 # ITB accesses system.cpu08.itb.read_hits 0 # DTB read hits system.cpu08.itb.read_misses 0 # DTB read misses system.cpu08.itb.read_acv 0 # DTB read access violations system.cpu08.itb.read_accesses 0 # DTB read accesses system.cpu08.itb.write_hits 0 # DTB write hits system.cpu08.itb.write_misses 0 # DTB write misses system.cpu08.itb.write_acv 0 # DTB write access violations system.cpu08.itb.write_accesses 0 # DTB write accesses system.cpu08.itb.data_hits 0 # DTB hits system.cpu08.itb.data_misses 0 # DTB misses system.cpu08.itb.data_acv 0 # DTB access violations system.cpu08.itb.data_accesses 0 # DTB accesses system.cpu08.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu08.numCycles 551 # number of cpu cycles simulated system.cpu08.numWorkItemsStarted 0 # number of work items this cpu started system.cpu08.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu08.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu08.fetch.Insts 10 # Number of instructions fetch has processed system.cpu08.fetch.Branches 5 # Number of branches that fetch encountered system.cpu08.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu08.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu08.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu08.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu08.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu08.fetch.CacheLines 3 # Number of cache lines fetched system.cpu08.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu08.fetch.branchRate 0.009074 # Number of branch fetches per cycle system.cpu08.fetch.rate 0.018149 # Number of inst fetches per cycle system.cpu08.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu08.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu08.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu08.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu08.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu08.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu08.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu08.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu08.rename.RunCycles 0 # Number of cycles rename is running system.cpu08.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu08.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu08.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu08.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu08.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu08.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu08.rename.serializingInsts 0 # count of serializing insts renamed system.cpu08.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu08.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu08.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu08.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu08.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu08.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu08.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu08.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu08.iq.iqInstsIssued 6 # Number of instructions issued system.cpu08.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu08.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu08.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu08.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu08.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu08.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu08.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu08.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu08.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu08.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu08.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu08.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu08.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu08.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu08.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu08.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu08.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu08.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu08.iq.FU_type_0::total 6 # Type of FU issued system.cpu08.iq.rate 0.010889 # Inst issue rate system.cpu08.iq.fu_busy_cnt 0 # FU busy when requested system.cpu08.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu08.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu08.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu08.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu08.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu08.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu08.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu08.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu08.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu08.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu08.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu08.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu08.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu08.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu08.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu08.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu08.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu08.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu08.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu08.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu08.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu08.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu08.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu08.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu08.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu08.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu08.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu08.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu08.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu08.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu08.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu08.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu08.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu08.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu08.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu08.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu08.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu08.iew.exec_swp 0 # number of swp insts executed system.cpu08.iew.exec_nop 1 # number of nop insts executed system.cpu08.iew.exec_refs 2 # number of memory reference insts executed system.cpu08.iew.exec_branches 1 # Number of branches executed system.cpu08.iew.exec_stores 0 # Number of stores executed system.cpu08.iew.exec_rate 0.010889 # Inst execution rate system.cpu08.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu08.iew.wb_count 5 # cumulative count of insts written-back system.cpu08.iew.wb_producers 1 # num instructions producing a value system.cpu08.iew.wb_consumers 1 # num instructions consuming a value system.cpu08.iew.wb_rate 0.009074 # insts written-back per cycle system.cpu08.iew.wb_fanout 1 # average fanout of values written-back system.cpu08.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu08.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu08.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu08.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu08.commit.committedInsts 1 # Number of instructions committed system.cpu08.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu08.commit.swp_count 0 # Number of s/w prefetches committed system.cpu08.commit.refs 1 # Number of memory references committed system.cpu08.commit.loads 1 # Number of loads committed system.cpu08.commit.membars 0 # Number of memory barriers committed system.cpu08.commit.branches 0 # Number of branches committed system.cpu08.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu08.commit.int_insts 1 # Number of committed integer instructions. system.cpu08.commit.function_calls 0 # Number of function calls committed. system.cpu08.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu08.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu08.commit.op_class_0::total 1 # Class of committed instruction system.cpu08.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu08.rob.rob_reads 60 # The number of ROB reads system.cpu08.rob.rob_writes 26 # The number of ROB writes system.cpu08.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu08.idleCycles 497 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu08.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu08.committedInsts 1 # Number of Instructions Simulated system.cpu08.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu08.cpi 551.000000 # CPI: Cycles Per Instruction system.cpu08.cpi_total 551.000000 # CPI: Total CPI of All Threads system.cpu08.ipc 0.001815 # IPC: Instructions Per Cycle system.cpu08.ipc_total 0.001815 # IPC: Total IPC of All Threads system.cpu08.int_regfile_reads 48 # number of integer regfile reads system.cpu08.int_regfile_writes 4 # number of integer regfile writes system.cpu08.fp_regfile_reads 32 # number of floating regfile reads system.cpu08.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu08.dcache.tags.replacements 0 # number of replacements system.cpu08.dcache.tags.tagsinuse 1.995826 # Cycle average of tags in use system.cpu08.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu08.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu08.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu08.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu08.dcache.tags.occ_blocks::cpu08.data 1.995826 # Average occupied blocks per requestor system.cpu08.dcache.tags.occ_percent::cpu08.data 0.003898 # Average percentage of cache occupancy system.cpu08.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu08.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu08.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu08.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu08.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu08.dcache.tags.data_accesses 210 # Number of data accesses system.cpu08.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu08.dcache.ReadReq_hits::switch_cpus08.data 50 # number of ReadReq hits system.cpu08.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu08.dcache.demand_hits::switch_cpus08.data 50 # number of demand (read+write) hits system.cpu08.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu08.dcache.overall_hits::switch_cpus08.data 50 # number of overall hits system.cpu08.dcache.overall_hits::total 50 # number of overall hits system.cpu08.dcache.ReadReq_misses::cpu08.data 2 # number of ReadReq misses system.cpu08.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu08.dcache.demand_misses::cpu08.data 2 # number of demand (read+write) misses system.cpu08.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu08.dcache.overall_misses::cpu08.data 2 # number of overall misses system.cpu08.dcache.overall_misses::total 2 # number of overall misses system.cpu08.dcache.ReadReq_miss_latency::cpu08.data 334500 # number of ReadReq miss cycles system.cpu08.dcache.ReadReq_miss_latency::total 334500 # number of ReadReq miss cycles system.cpu08.dcache.demand_miss_latency::cpu08.data 334500 # number of demand (read+write) miss cycles system.cpu08.dcache.demand_miss_latency::total 334500 # number of demand (read+write) miss cycles system.cpu08.dcache.overall_miss_latency::cpu08.data 334500 # number of overall miss cycles system.cpu08.dcache.overall_miss_latency::total 334500 # number of overall miss cycles system.cpu08.dcache.ReadReq_accesses::cpu08.data 2 # number of ReadReq accesses(hits+misses) system.cpu08.dcache.ReadReq_accesses::switch_cpus08.data 50 # number of ReadReq accesses(hits+misses) system.cpu08.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu08.dcache.demand_accesses::cpu08.data 2 # number of demand (read+write) accesses system.cpu08.dcache.demand_accesses::switch_cpus08.data 50 # number of demand (read+write) accesses system.cpu08.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu08.dcache.overall_accesses::cpu08.data 2 # number of overall (read+write) accesses system.cpu08.dcache.overall_accesses::switch_cpus08.data 50 # number of overall (read+write) accesses system.cpu08.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu08.dcache.ReadReq_miss_rate::cpu08.data 1 # miss rate for ReadReq accesses system.cpu08.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu08.dcache.demand_miss_rate::cpu08.data 1 # miss rate for demand accesses system.cpu08.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu08.dcache.overall_miss_rate::cpu08.data 1 # miss rate for overall accesses system.cpu08.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu08.dcache.ReadReq_avg_miss_latency::cpu08.data 167250 # average ReadReq miss latency system.cpu08.dcache.ReadReq_avg_miss_latency::total 167250 # average ReadReq miss latency system.cpu08.dcache.demand_avg_miss_latency::cpu08.data 167250 # average overall miss latency system.cpu08.dcache.demand_avg_miss_latency::total 167250 # average overall miss latency system.cpu08.dcache.overall_avg_miss_latency::cpu08.data 167250 # average overall miss latency system.cpu08.dcache.overall_avg_miss_latency::total 167250 # average overall miss latency system.cpu08.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu08.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu08.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu08.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu08.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu08.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu08.dcache.ReadReq_mshr_misses::cpu08.data 2 # number of ReadReq MSHR misses system.cpu08.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu08.dcache.demand_mshr_misses::cpu08.data 2 # number of demand (read+write) MSHR misses system.cpu08.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu08.dcache.overall_mshr_misses::cpu08.data 2 # number of overall MSHR misses system.cpu08.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu08.dcache.ReadReq_mshr_miss_latency::cpu08.data 332500 # number of ReadReq MSHR miss cycles system.cpu08.dcache.ReadReq_mshr_miss_latency::total 332500 # number of ReadReq MSHR miss cycles system.cpu08.dcache.demand_mshr_miss_latency::cpu08.data 332500 # number of demand (read+write) MSHR miss cycles system.cpu08.dcache.demand_mshr_miss_latency::total 332500 # number of demand (read+write) MSHR miss cycles system.cpu08.dcache.overall_mshr_miss_latency::cpu08.data 332500 # number of overall MSHR miss cycles system.cpu08.dcache.overall_mshr_miss_latency::total 332500 # number of overall MSHR miss cycles system.cpu08.dcache.ReadReq_mshr_miss_rate::cpu08.data 1 # mshr miss rate for ReadReq accesses system.cpu08.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu08.dcache.demand_mshr_miss_rate::cpu08.data 1 # mshr miss rate for demand accesses system.cpu08.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu08.dcache.overall_mshr_miss_rate::cpu08.data 1 # mshr miss rate for overall accesses system.cpu08.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu08.dcache.ReadReq_avg_mshr_miss_latency::cpu08.data 166250 # average ReadReq mshr miss latency system.cpu08.dcache.ReadReq_avg_mshr_miss_latency::total 166250 # average ReadReq mshr miss latency system.cpu08.dcache.demand_avg_mshr_miss_latency::cpu08.data 166250 # average overall mshr miss latency system.cpu08.dcache.demand_avg_mshr_miss_latency::total 166250 # average overall mshr miss latency system.cpu08.dcache.overall_avg_mshr_miss_latency::cpu08.data 166250 # average overall mshr miss latency system.cpu08.dcache.overall_avg_mshr_miss_latency::total 166250 # average overall mshr miss latency system.cpu08.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu08.icache.tags.replacements 0 # number of replacements system.cpu08.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu08.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu08.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu08.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu08.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu08.icache.tags.occ_blocks::cpu08.inst 1.995860 # Average occupied blocks per requestor system.cpu08.icache.tags.occ_percent::cpu08.inst 0.003898 # Average percentage of cache occupancy system.cpu08.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu08.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu08.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu08.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu08.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu08.icache.tags.data_accesses 622 # Number of data accesses system.cpu08.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu08.icache.ReadReq_hits::cpu08.inst 1 # number of ReadReq hits system.cpu08.icache.ReadReq_hits::switch_cpus08.inst 152 # number of ReadReq hits system.cpu08.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu08.icache.demand_hits::cpu08.inst 1 # number of demand (read+write) hits system.cpu08.icache.demand_hits::switch_cpus08.inst 152 # number of demand (read+write) hits system.cpu08.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu08.icache.overall_hits::cpu08.inst 1 # number of overall hits system.cpu08.icache.overall_hits::switch_cpus08.inst 152 # number of overall hits system.cpu08.icache.overall_hits::total 153 # number of overall hits system.cpu08.icache.ReadReq_misses::cpu08.inst 2 # number of ReadReq misses system.cpu08.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu08.icache.demand_misses::cpu08.inst 2 # number of demand (read+write) misses system.cpu08.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu08.icache.overall_misses::cpu08.inst 2 # number of overall misses system.cpu08.icache.overall_misses::total 2 # number of overall misses system.cpu08.icache.ReadReq_miss_latency::cpu08.inst 164500 # number of ReadReq miss cycles system.cpu08.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu08.icache.demand_miss_latency::cpu08.inst 164500 # number of demand (read+write) miss cycles system.cpu08.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu08.icache.overall_miss_latency::cpu08.inst 164500 # number of overall miss cycles system.cpu08.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu08.icache.ReadReq_accesses::cpu08.inst 3 # number of ReadReq accesses(hits+misses) system.cpu08.icache.ReadReq_accesses::switch_cpus08.inst 152 # number of ReadReq accesses(hits+misses) system.cpu08.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu08.icache.demand_accesses::cpu08.inst 3 # number of demand (read+write) accesses system.cpu08.icache.demand_accesses::switch_cpus08.inst 152 # number of demand (read+write) accesses system.cpu08.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu08.icache.overall_accesses::cpu08.inst 3 # number of overall (read+write) accesses system.cpu08.icache.overall_accesses::switch_cpus08.inst 152 # number of overall (read+write) accesses system.cpu08.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu08.icache.ReadReq_miss_rate::cpu08.inst 0.666667 # miss rate for ReadReq accesses system.cpu08.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu08.icache.demand_miss_rate::cpu08.inst 0.666667 # miss rate for demand accesses system.cpu08.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu08.icache.overall_miss_rate::cpu08.inst 0.666667 # miss rate for overall accesses system.cpu08.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu08.icache.ReadReq_avg_miss_latency::cpu08.inst 82250 # average ReadReq miss latency system.cpu08.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu08.icache.demand_avg_miss_latency::cpu08.inst 82250 # average overall miss latency system.cpu08.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu08.icache.overall_avg_miss_latency::cpu08.inst 82250 # average overall miss latency system.cpu08.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu08.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu08.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu08.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu08.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu08.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu08.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu08.icache.ReadReq_mshr_misses::cpu08.inst 2 # number of ReadReq MSHR misses system.cpu08.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu08.icache.demand_mshr_misses::cpu08.inst 2 # number of demand (read+write) MSHR misses system.cpu08.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu08.icache.overall_mshr_misses::cpu08.inst 2 # number of overall MSHR misses system.cpu08.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu08.icache.ReadReq_mshr_miss_latency::cpu08.inst 162500 # number of ReadReq MSHR miss cycles system.cpu08.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu08.icache.demand_mshr_miss_latency::cpu08.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu08.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu08.icache.overall_mshr_miss_latency::cpu08.inst 162500 # number of overall MSHR miss cycles system.cpu08.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu08.icache.ReadReq_mshr_miss_rate::cpu08.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu08.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu08.icache.demand_mshr_miss_rate::cpu08.inst 0.666667 # mshr miss rate for demand accesses system.cpu08.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu08.icache.overall_mshr_miss_rate::cpu08.inst 0.666667 # mshr miss rate for overall accesses system.cpu08.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu08.icache.ReadReq_avg_mshr_miss_latency::cpu08.inst 81250 # average ReadReq mshr miss latency system.cpu08.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu08.icache.demand_avg_mshr_miss_latency::cpu08.inst 81250 # average overall mshr miss latency system.cpu08.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu08.icache.overall_avg_mshr_miss_latency::cpu08.inst 81250 # average overall mshr miss latency system.cpu08.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu09.branchPred.lookups 5 # Number of BP lookups system.cpu09.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu09.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu09.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu09.branchPred.BTBHits 0 # Number of BTB hits system.cpu09.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu09.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu09.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu09.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu09.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu09.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu09.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu09.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu09.dtb.fetch_hits 0 # ITB hits system.cpu09.dtb.fetch_misses 0 # ITB misses system.cpu09.dtb.fetch_acv 0 # ITB acv system.cpu09.dtb.fetch_accesses 0 # ITB accesses system.cpu09.dtb.read_hits 2 # DTB read hits system.cpu09.dtb.read_misses 0 # DTB read misses system.cpu09.dtb.read_acv 0 # DTB read access violations system.cpu09.dtb.read_accesses 0 # DTB read accesses system.cpu09.dtb.write_hits 0 # DTB write hits system.cpu09.dtb.write_misses 0 # DTB write misses system.cpu09.dtb.write_acv 0 # DTB write access violations system.cpu09.dtb.write_accesses 0 # DTB write accesses system.cpu09.dtb.data_hits 2 # DTB hits system.cpu09.dtb.data_misses 0 # DTB misses system.cpu09.dtb.data_acv 0 # DTB access violations system.cpu09.dtb.data_accesses 0 # DTB accesses system.cpu09.itb.fetch_hits 0 # ITB hits system.cpu09.itb.fetch_misses 1 # ITB misses system.cpu09.itb.fetch_acv 0 # ITB acv system.cpu09.itb.fetch_accesses 1 # ITB accesses system.cpu09.itb.read_hits 0 # DTB read hits system.cpu09.itb.read_misses 0 # DTB read misses system.cpu09.itb.read_acv 0 # DTB read access violations system.cpu09.itb.read_accesses 0 # DTB read accesses system.cpu09.itb.write_hits 0 # DTB write hits system.cpu09.itb.write_misses 0 # DTB write misses system.cpu09.itb.write_acv 0 # DTB write access violations system.cpu09.itb.write_accesses 0 # DTB write accesses system.cpu09.itb.data_hits 0 # DTB hits system.cpu09.itb.data_misses 0 # DTB misses system.cpu09.itb.data_acv 0 # DTB access violations system.cpu09.itb.data_accesses 0 # DTB accesses system.cpu09.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu09.numCycles 561 # number of cpu cycles simulated system.cpu09.numWorkItemsStarted 0 # number of work items this cpu started system.cpu09.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu09.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu09.fetch.Insts 10 # Number of instructions fetch has processed system.cpu09.fetch.Branches 5 # Number of branches that fetch encountered system.cpu09.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu09.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu09.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu09.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu09.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu09.fetch.CacheLines 3 # Number of cache lines fetched system.cpu09.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu09.fetch.branchRate 0.008913 # Number of branch fetches per cycle system.cpu09.fetch.rate 0.017825 # Number of inst fetches per cycle system.cpu09.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu09.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu09.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu09.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu09.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu09.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu09.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu09.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu09.rename.RunCycles 0 # Number of cycles rename is running system.cpu09.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu09.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu09.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu09.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu09.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu09.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu09.rename.serializingInsts 0 # count of serializing insts renamed system.cpu09.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu09.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu09.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu09.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu09.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu09.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu09.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu09.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu09.iq.iqInstsIssued 6 # Number of instructions issued system.cpu09.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu09.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu09.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu09.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu09.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu09.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu09.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu09.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu09.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu09.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu09.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu09.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu09.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu09.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu09.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu09.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu09.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu09.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu09.iq.FU_type_0::total 6 # Type of FU issued system.cpu09.iq.rate 0.010695 # Inst issue rate system.cpu09.iq.fu_busy_cnt 0 # FU busy when requested system.cpu09.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu09.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu09.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu09.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu09.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu09.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu09.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu09.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu09.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu09.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu09.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu09.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu09.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu09.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu09.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu09.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu09.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu09.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu09.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu09.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu09.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu09.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu09.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu09.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu09.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu09.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu09.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu09.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu09.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu09.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu09.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu09.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu09.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu09.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu09.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu09.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu09.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu09.iew.exec_swp 0 # number of swp insts executed system.cpu09.iew.exec_nop 1 # number of nop insts executed system.cpu09.iew.exec_refs 2 # number of memory reference insts executed system.cpu09.iew.exec_branches 1 # Number of branches executed system.cpu09.iew.exec_stores 0 # Number of stores executed system.cpu09.iew.exec_rate 0.010695 # Inst execution rate system.cpu09.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu09.iew.wb_count 5 # cumulative count of insts written-back system.cpu09.iew.wb_producers 1 # num instructions producing a value system.cpu09.iew.wb_consumers 1 # num instructions consuming a value system.cpu09.iew.wb_rate 0.008913 # insts written-back per cycle system.cpu09.iew.wb_fanout 1 # average fanout of values written-back system.cpu09.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu09.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu09.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu09.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu09.commit.committedInsts 1 # Number of instructions committed system.cpu09.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu09.commit.swp_count 0 # Number of s/w prefetches committed system.cpu09.commit.refs 1 # Number of memory references committed system.cpu09.commit.loads 1 # Number of loads committed system.cpu09.commit.membars 0 # Number of memory barriers committed system.cpu09.commit.branches 0 # Number of branches committed system.cpu09.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu09.commit.int_insts 1 # Number of committed integer instructions. system.cpu09.commit.function_calls 0 # Number of function calls committed. system.cpu09.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu09.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu09.commit.op_class_0::total 1 # Class of committed instruction system.cpu09.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu09.rob.rob_reads 60 # The number of ROB reads system.cpu09.rob.rob_writes 26 # The number of ROB writes system.cpu09.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu09.idleCycles 507 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu09.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu09.committedInsts 1 # Number of Instructions Simulated system.cpu09.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu09.cpi 561.000000 # CPI: Cycles Per Instruction system.cpu09.cpi_total 561.000000 # CPI: Total CPI of All Threads system.cpu09.ipc 0.001783 # IPC: Instructions Per Cycle system.cpu09.ipc_total 0.001783 # IPC: Total IPC of All Threads system.cpu09.int_regfile_reads 48 # number of integer regfile reads system.cpu09.int_regfile_writes 4 # number of integer regfile writes system.cpu09.fp_regfile_reads 32 # number of floating regfile reads system.cpu09.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu09.dcache.tags.replacements 0 # number of replacements system.cpu09.dcache.tags.tagsinuse 1.995825 # Cycle average of tags in use system.cpu09.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu09.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu09.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu09.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu09.dcache.tags.occ_blocks::cpu09.data 1.995825 # Average occupied blocks per requestor system.cpu09.dcache.tags.occ_percent::cpu09.data 0.003898 # Average percentage of cache occupancy system.cpu09.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu09.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu09.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu09.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu09.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu09.dcache.tags.data_accesses 210 # Number of data accesses system.cpu09.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu09.dcache.ReadReq_hits::switch_cpus09.data 50 # number of ReadReq hits system.cpu09.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu09.dcache.demand_hits::switch_cpus09.data 50 # number of demand (read+write) hits system.cpu09.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu09.dcache.overall_hits::switch_cpus09.data 50 # number of overall hits system.cpu09.dcache.overall_hits::total 50 # number of overall hits system.cpu09.dcache.ReadReq_misses::cpu09.data 2 # number of ReadReq misses system.cpu09.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu09.dcache.demand_misses::cpu09.data 2 # number of demand (read+write) misses system.cpu09.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu09.dcache.overall_misses::cpu09.data 2 # number of overall misses system.cpu09.dcache.overall_misses::total 2 # number of overall misses system.cpu09.dcache.ReadReq_miss_latency::cpu09.data 339500 # number of ReadReq miss cycles system.cpu09.dcache.ReadReq_miss_latency::total 339500 # number of ReadReq miss cycles system.cpu09.dcache.demand_miss_latency::cpu09.data 339500 # number of demand (read+write) miss cycles system.cpu09.dcache.demand_miss_latency::total 339500 # number of demand (read+write) miss cycles system.cpu09.dcache.overall_miss_latency::cpu09.data 339500 # number of overall miss cycles system.cpu09.dcache.overall_miss_latency::total 339500 # number of overall miss cycles system.cpu09.dcache.ReadReq_accesses::cpu09.data 2 # number of ReadReq accesses(hits+misses) system.cpu09.dcache.ReadReq_accesses::switch_cpus09.data 50 # number of ReadReq accesses(hits+misses) system.cpu09.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu09.dcache.demand_accesses::cpu09.data 2 # number of demand (read+write) accesses system.cpu09.dcache.demand_accesses::switch_cpus09.data 50 # number of demand (read+write) accesses system.cpu09.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu09.dcache.overall_accesses::cpu09.data 2 # number of overall (read+write) accesses system.cpu09.dcache.overall_accesses::switch_cpus09.data 50 # number of overall (read+write) accesses system.cpu09.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu09.dcache.ReadReq_miss_rate::cpu09.data 1 # miss rate for ReadReq accesses system.cpu09.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu09.dcache.demand_miss_rate::cpu09.data 1 # miss rate for demand accesses system.cpu09.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu09.dcache.overall_miss_rate::cpu09.data 1 # miss rate for overall accesses system.cpu09.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu09.dcache.ReadReq_avg_miss_latency::cpu09.data 169750 # average ReadReq miss latency system.cpu09.dcache.ReadReq_avg_miss_latency::total 169750 # average ReadReq miss latency system.cpu09.dcache.demand_avg_miss_latency::cpu09.data 169750 # average overall miss latency system.cpu09.dcache.demand_avg_miss_latency::total 169750 # average overall miss latency system.cpu09.dcache.overall_avg_miss_latency::cpu09.data 169750 # average overall miss latency system.cpu09.dcache.overall_avg_miss_latency::total 169750 # average overall miss latency system.cpu09.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu09.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu09.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu09.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu09.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu09.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu09.dcache.ReadReq_mshr_misses::cpu09.data 2 # number of ReadReq MSHR misses system.cpu09.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu09.dcache.demand_mshr_misses::cpu09.data 2 # number of demand (read+write) MSHR misses system.cpu09.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu09.dcache.overall_mshr_misses::cpu09.data 2 # number of overall MSHR misses system.cpu09.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu09.dcache.ReadReq_mshr_miss_latency::cpu09.data 337500 # number of ReadReq MSHR miss cycles system.cpu09.dcache.ReadReq_mshr_miss_latency::total 337500 # number of ReadReq MSHR miss cycles system.cpu09.dcache.demand_mshr_miss_latency::cpu09.data 337500 # number of demand (read+write) MSHR miss cycles system.cpu09.dcache.demand_mshr_miss_latency::total 337500 # number of demand (read+write) MSHR miss cycles system.cpu09.dcache.overall_mshr_miss_latency::cpu09.data 337500 # number of overall MSHR miss cycles system.cpu09.dcache.overall_mshr_miss_latency::total 337500 # number of overall MSHR miss cycles system.cpu09.dcache.ReadReq_mshr_miss_rate::cpu09.data 1 # mshr miss rate for ReadReq accesses system.cpu09.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu09.dcache.demand_mshr_miss_rate::cpu09.data 1 # mshr miss rate for demand accesses system.cpu09.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu09.dcache.overall_mshr_miss_rate::cpu09.data 1 # mshr miss rate for overall accesses system.cpu09.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu09.dcache.ReadReq_avg_mshr_miss_latency::cpu09.data 168750 # average ReadReq mshr miss latency system.cpu09.dcache.ReadReq_avg_mshr_miss_latency::total 168750 # average ReadReq mshr miss latency system.cpu09.dcache.demand_avg_mshr_miss_latency::cpu09.data 168750 # average overall mshr miss latency system.cpu09.dcache.demand_avg_mshr_miss_latency::total 168750 # average overall mshr miss latency system.cpu09.dcache.overall_avg_mshr_miss_latency::cpu09.data 168750 # average overall mshr miss latency system.cpu09.dcache.overall_avg_mshr_miss_latency::total 168750 # average overall mshr miss latency system.cpu09.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu09.icache.tags.replacements 0 # number of replacements system.cpu09.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu09.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu09.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu09.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu09.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu09.icache.tags.occ_blocks::cpu09.inst 1.995860 # Average occupied blocks per requestor system.cpu09.icache.tags.occ_percent::cpu09.inst 0.003898 # Average percentage of cache occupancy system.cpu09.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu09.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu09.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu09.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu09.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu09.icache.tags.data_accesses 622 # Number of data accesses system.cpu09.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu09.icache.ReadReq_hits::cpu09.inst 1 # number of ReadReq hits system.cpu09.icache.ReadReq_hits::switch_cpus09.inst 152 # number of ReadReq hits system.cpu09.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu09.icache.demand_hits::cpu09.inst 1 # number of demand (read+write) hits system.cpu09.icache.demand_hits::switch_cpus09.inst 152 # number of demand (read+write) hits system.cpu09.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu09.icache.overall_hits::cpu09.inst 1 # number of overall hits system.cpu09.icache.overall_hits::switch_cpus09.inst 152 # number of overall hits system.cpu09.icache.overall_hits::total 153 # number of overall hits system.cpu09.icache.ReadReq_misses::cpu09.inst 2 # number of ReadReq misses system.cpu09.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu09.icache.demand_misses::cpu09.inst 2 # number of demand (read+write) misses system.cpu09.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu09.icache.overall_misses::cpu09.inst 2 # number of overall misses system.cpu09.icache.overall_misses::total 2 # number of overall misses system.cpu09.icache.ReadReq_miss_latency::cpu09.inst 164500 # number of ReadReq miss cycles system.cpu09.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu09.icache.demand_miss_latency::cpu09.inst 164500 # number of demand (read+write) miss cycles system.cpu09.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu09.icache.overall_miss_latency::cpu09.inst 164500 # number of overall miss cycles system.cpu09.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu09.icache.ReadReq_accesses::cpu09.inst 3 # number of ReadReq accesses(hits+misses) system.cpu09.icache.ReadReq_accesses::switch_cpus09.inst 152 # number of ReadReq accesses(hits+misses) system.cpu09.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu09.icache.demand_accesses::cpu09.inst 3 # number of demand (read+write) accesses system.cpu09.icache.demand_accesses::switch_cpus09.inst 152 # number of demand (read+write) accesses system.cpu09.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu09.icache.overall_accesses::cpu09.inst 3 # number of overall (read+write) accesses system.cpu09.icache.overall_accesses::switch_cpus09.inst 152 # number of overall (read+write) accesses system.cpu09.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu09.icache.ReadReq_miss_rate::cpu09.inst 0.666667 # miss rate for ReadReq accesses system.cpu09.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu09.icache.demand_miss_rate::cpu09.inst 0.666667 # miss rate for demand accesses system.cpu09.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu09.icache.overall_miss_rate::cpu09.inst 0.666667 # miss rate for overall accesses system.cpu09.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu09.icache.ReadReq_avg_miss_latency::cpu09.inst 82250 # average ReadReq miss latency system.cpu09.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu09.icache.demand_avg_miss_latency::cpu09.inst 82250 # average overall miss latency system.cpu09.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu09.icache.overall_avg_miss_latency::cpu09.inst 82250 # average overall miss latency system.cpu09.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu09.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu09.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu09.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu09.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu09.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu09.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu09.icache.ReadReq_mshr_misses::cpu09.inst 2 # number of ReadReq MSHR misses system.cpu09.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu09.icache.demand_mshr_misses::cpu09.inst 2 # number of demand (read+write) MSHR misses system.cpu09.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu09.icache.overall_mshr_misses::cpu09.inst 2 # number of overall MSHR misses system.cpu09.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu09.icache.ReadReq_mshr_miss_latency::cpu09.inst 162500 # number of ReadReq MSHR miss cycles system.cpu09.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu09.icache.demand_mshr_miss_latency::cpu09.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu09.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu09.icache.overall_mshr_miss_latency::cpu09.inst 162500 # number of overall MSHR miss cycles system.cpu09.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu09.icache.ReadReq_mshr_miss_rate::cpu09.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu09.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu09.icache.demand_mshr_miss_rate::cpu09.inst 0.666667 # mshr miss rate for demand accesses system.cpu09.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu09.icache.overall_mshr_miss_rate::cpu09.inst 0.666667 # mshr miss rate for overall accesses system.cpu09.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu09.icache.ReadReq_avg_mshr_miss_latency::cpu09.inst 81250 # average ReadReq mshr miss latency system.cpu09.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu09.icache.demand_avg_mshr_miss_latency::cpu09.inst 81250 # average overall mshr miss latency system.cpu09.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu09.icache.overall_avg_mshr_miss_latency::cpu09.inst 81250 # average overall mshr miss latency system.cpu09.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu10.branchPred.lookups 5 # Number of BP lookups system.cpu10.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu10.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu10.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu10.branchPred.BTBHits 0 # Number of BTB hits system.cpu10.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu10.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu10.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu10.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu10.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu10.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu10.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu10.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu10.dtb.fetch_hits 0 # ITB hits system.cpu10.dtb.fetch_misses 0 # ITB misses system.cpu10.dtb.fetch_acv 0 # ITB acv system.cpu10.dtb.fetch_accesses 0 # ITB accesses system.cpu10.dtb.read_hits 2 # DTB read hits system.cpu10.dtb.read_misses 0 # DTB read misses system.cpu10.dtb.read_acv 0 # DTB read access violations system.cpu10.dtb.read_accesses 0 # DTB read accesses system.cpu10.dtb.write_hits 0 # DTB write hits system.cpu10.dtb.write_misses 0 # DTB write misses system.cpu10.dtb.write_acv 0 # DTB write access violations system.cpu10.dtb.write_accesses 0 # DTB write accesses system.cpu10.dtb.data_hits 2 # DTB hits system.cpu10.dtb.data_misses 0 # DTB misses system.cpu10.dtb.data_acv 0 # DTB access violations system.cpu10.dtb.data_accesses 0 # DTB accesses system.cpu10.itb.fetch_hits 0 # ITB hits system.cpu10.itb.fetch_misses 1 # ITB misses system.cpu10.itb.fetch_acv 0 # ITB acv system.cpu10.itb.fetch_accesses 1 # ITB accesses system.cpu10.itb.read_hits 0 # DTB read hits system.cpu10.itb.read_misses 0 # DTB read misses system.cpu10.itb.read_acv 0 # DTB read access violations system.cpu10.itb.read_accesses 0 # DTB read accesses system.cpu10.itb.write_hits 0 # DTB write hits system.cpu10.itb.write_misses 0 # DTB write misses system.cpu10.itb.write_acv 0 # DTB write access violations system.cpu10.itb.write_accesses 0 # DTB write accesses system.cpu10.itb.data_hits 0 # DTB hits system.cpu10.itb.data_misses 0 # DTB misses system.cpu10.itb.data_acv 0 # DTB access violations system.cpu10.itb.data_accesses 0 # DTB accesses system.cpu10.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu10.numCycles 571 # number of cpu cycles simulated system.cpu10.numWorkItemsStarted 0 # number of work items this cpu started system.cpu10.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu10.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu10.fetch.Insts 10 # Number of instructions fetch has processed system.cpu10.fetch.Branches 5 # Number of branches that fetch encountered system.cpu10.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu10.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu10.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu10.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu10.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu10.fetch.CacheLines 3 # Number of cache lines fetched system.cpu10.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu10.fetch.branchRate 0.008757 # Number of branch fetches per cycle system.cpu10.fetch.rate 0.017513 # Number of inst fetches per cycle system.cpu10.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu10.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu10.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu10.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu10.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu10.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu10.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu10.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu10.rename.RunCycles 0 # Number of cycles rename is running system.cpu10.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu10.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu10.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu10.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu10.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu10.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu10.rename.serializingInsts 0 # count of serializing insts renamed system.cpu10.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu10.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu10.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu10.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu10.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu10.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu10.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu10.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu10.iq.iqInstsIssued 6 # Number of instructions issued system.cpu10.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu10.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu10.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu10.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu10.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu10.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu10.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu10.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu10.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu10.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu10.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu10.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu10.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu10.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu10.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu10.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu10.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu10.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu10.iq.FU_type_0::total 6 # Type of FU issued system.cpu10.iq.rate 0.010508 # Inst issue rate system.cpu10.iq.fu_busy_cnt 0 # FU busy when requested system.cpu10.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu10.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu10.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu10.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu10.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu10.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu10.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu10.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu10.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu10.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu10.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu10.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu10.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu10.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu10.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu10.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu10.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu10.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu10.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu10.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu10.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu10.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu10.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu10.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu10.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu10.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu10.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu10.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu10.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu10.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu10.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu10.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu10.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu10.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu10.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu10.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu10.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu10.iew.exec_swp 0 # number of swp insts executed system.cpu10.iew.exec_nop 1 # number of nop insts executed system.cpu10.iew.exec_refs 2 # number of memory reference insts executed system.cpu10.iew.exec_branches 1 # Number of branches executed system.cpu10.iew.exec_stores 0 # Number of stores executed system.cpu10.iew.exec_rate 0.010508 # Inst execution rate system.cpu10.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu10.iew.wb_count 5 # cumulative count of insts written-back system.cpu10.iew.wb_producers 1 # num instructions producing a value system.cpu10.iew.wb_consumers 1 # num instructions consuming a value system.cpu10.iew.wb_rate 0.008757 # insts written-back per cycle system.cpu10.iew.wb_fanout 1 # average fanout of values written-back system.cpu10.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu10.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu10.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu10.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu10.commit.committedInsts 1 # Number of instructions committed system.cpu10.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu10.commit.swp_count 0 # Number of s/w prefetches committed system.cpu10.commit.refs 1 # Number of memory references committed system.cpu10.commit.loads 1 # Number of loads committed system.cpu10.commit.membars 0 # Number of memory barriers committed system.cpu10.commit.branches 0 # Number of branches committed system.cpu10.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu10.commit.int_insts 1 # Number of committed integer instructions. system.cpu10.commit.function_calls 0 # Number of function calls committed. system.cpu10.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu10.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu10.commit.op_class_0::total 1 # Class of committed instruction system.cpu10.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu10.rob.rob_reads 60 # The number of ROB reads system.cpu10.rob.rob_writes 26 # The number of ROB writes system.cpu10.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu10.idleCycles 517 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu10.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu10.committedInsts 1 # Number of Instructions Simulated system.cpu10.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu10.cpi 571.000000 # CPI: Cycles Per Instruction system.cpu10.cpi_total 571.000000 # CPI: Total CPI of All Threads system.cpu10.ipc 0.001751 # IPC: Instructions Per Cycle system.cpu10.ipc_total 0.001751 # IPC: Total IPC of All Threads system.cpu10.int_regfile_reads 48 # number of integer regfile reads system.cpu10.int_regfile_writes 4 # number of integer regfile writes system.cpu10.fp_regfile_reads 32 # number of floating regfile reads system.cpu10.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu10.dcache.tags.replacements 0 # number of replacements system.cpu10.dcache.tags.tagsinuse 1.995825 # Cycle average of tags in use system.cpu10.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu10.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu10.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu10.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu10.dcache.tags.occ_blocks::cpu10.data 1.995825 # Average occupied blocks per requestor system.cpu10.dcache.tags.occ_percent::cpu10.data 0.003898 # Average percentage of cache occupancy system.cpu10.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu10.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu10.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu10.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu10.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu10.dcache.tags.data_accesses 210 # Number of data accesses system.cpu10.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu10.dcache.ReadReq_hits::switch_cpus10.data 50 # number of ReadReq hits system.cpu10.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu10.dcache.demand_hits::switch_cpus10.data 50 # number of demand (read+write) hits system.cpu10.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu10.dcache.overall_hits::switch_cpus10.data 50 # number of overall hits system.cpu10.dcache.overall_hits::total 50 # number of overall hits system.cpu10.dcache.ReadReq_misses::cpu10.data 2 # number of ReadReq misses system.cpu10.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu10.dcache.demand_misses::cpu10.data 2 # number of demand (read+write) misses system.cpu10.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu10.dcache.overall_misses::cpu10.data 2 # number of overall misses system.cpu10.dcache.overall_misses::total 2 # number of overall misses system.cpu10.dcache.ReadReq_miss_latency::cpu10.data 344500 # number of ReadReq miss cycles system.cpu10.dcache.ReadReq_miss_latency::total 344500 # number of ReadReq miss cycles system.cpu10.dcache.demand_miss_latency::cpu10.data 344500 # number of demand (read+write) miss cycles system.cpu10.dcache.demand_miss_latency::total 344500 # number of demand (read+write) miss cycles system.cpu10.dcache.overall_miss_latency::cpu10.data 344500 # number of overall miss cycles system.cpu10.dcache.overall_miss_latency::total 344500 # number of overall miss cycles system.cpu10.dcache.ReadReq_accesses::cpu10.data 2 # number of ReadReq accesses(hits+misses) system.cpu10.dcache.ReadReq_accesses::switch_cpus10.data 50 # number of ReadReq accesses(hits+misses) system.cpu10.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu10.dcache.demand_accesses::cpu10.data 2 # number of demand (read+write) accesses system.cpu10.dcache.demand_accesses::switch_cpus10.data 50 # number of demand (read+write) accesses system.cpu10.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu10.dcache.overall_accesses::cpu10.data 2 # number of overall (read+write) accesses system.cpu10.dcache.overall_accesses::switch_cpus10.data 50 # number of overall (read+write) accesses system.cpu10.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu10.dcache.ReadReq_miss_rate::cpu10.data 1 # miss rate for ReadReq accesses system.cpu10.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu10.dcache.demand_miss_rate::cpu10.data 1 # miss rate for demand accesses system.cpu10.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu10.dcache.overall_miss_rate::cpu10.data 1 # miss rate for overall accesses system.cpu10.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu10.dcache.ReadReq_avg_miss_latency::cpu10.data 172250 # average ReadReq miss latency system.cpu10.dcache.ReadReq_avg_miss_latency::total 172250 # average ReadReq miss latency system.cpu10.dcache.demand_avg_miss_latency::cpu10.data 172250 # average overall miss latency system.cpu10.dcache.demand_avg_miss_latency::total 172250 # average overall miss latency system.cpu10.dcache.overall_avg_miss_latency::cpu10.data 172250 # average overall miss latency system.cpu10.dcache.overall_avg_miss_latency::total 172250 # average overall miss latency system.cpu10.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu10.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu10.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu10.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu10.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu10.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu10.dcache.ReadReq_mshr_misses::cpu10.data 2 # number of ReadReq MSHR misses system.cpu10.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu10.dcache.demand_mshr_misses::cpu10.data 2 # number of demand (read+write) MSHR misses system.cpu10.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu10.dcache.overall_mshr_misses::cpu10.data 2 # number of overall MSHR misses system.cpu10.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu10.dcache.ReadReq_mshr_miss_latency::cpu10.data 342500 # number of ReadReq MSHR miss cycles system.cpu10.dcache.ReadReq_mshr_miss_latency::total 342500 # number of ReadReq MSHR miss cycles system.cpu10.dcache.demand_mshr_miss_latency::cpu10.data 342500 # number of demand (read+write) MSHR miss cycles system.cpu10.dcache.demand_mshr_miss_latency::total 342500 # number of demand (read+write) MSHR miss cycles system.cpu10.dcache.overall_mshr_miss_latency::cpu10.data 342500 # number of overall MSHR miss cycles system.cpu10.dcache.overall_mshr_miss_latency::total 342500 # number of overall MSHR miss cycles system.cpu10.dcache.ReadReq_mshr_miss_rate::cpu10.data 1 # mshr miss rate for ReadReq accesses system.cpu10.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu10.dcache.demand_mshr_miss_rate::cpu10.data 1 # mshr miss rate for demand accesses system.cpu10.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu10.dcache.overall_mshr_miss_rate::cpu10.data 1 # mshr miss rate for overall accesses system.cpu10.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu10.dcache.ReadReq_avg_mshr_miss_latency::cpu10.data 171250 # average ReadReq mshr miss latency system.cpu10.dcache.ReadReq_avg_mshr_miss_latency::total 171250 # average ReadReq mshr miss latency system.cpu10.dcache.demand_avg_mshr_miss_latency::cpu10.data 171250 # average overall mshr miss latency system.cpu10.dcache.demand_avg_mshr_miss_latency::total 171250 # average overall mshr miss latency system.cpu10.dcache.overall_avg_mshr_miss_latency::cpu10.data 171250 # average overall mshr miss latency system.cpu10.dcache.overall_avg_mshr_miss_latency::total 171250 # average overall mshr miss latency system.cpu10.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu10.icache.tags.replacements 0 # number of replacements system.cpu10.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu10.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu10.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu10.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu10.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu10.icache.tags.occ_blocks::cpu10.inst 1.995860 # Average occupied blocks per requestor system.cpu10.icache.tags.occ_percent::cpu10.inst 0.003898 # Average percentage of cache occupancy system.cpu10.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu10.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu10.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu10.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu10.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu10.icache.tags.data_accesses 622 # Number of data accesses system.cpu10.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu10.icache.ReadReq_hits::cpu10.inst 1 # number of ReadReq hits system.cpu10.icache.ReadReq_hits::switch_cpus10.inst 152 # number of ReadReq hits system.cpu10.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu10.icache.demand_hits::cpu10.inst 1 # number of demand (read+write) hits system.cpu10.icache.demand_hits::switch_cpus10.inst 152 # number of demand (read+write) hits system.cpu10.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu10.icache.overall_hits::cpu10.inst 1 # number of overall hits system.cpu10.icache.overall_hits::switch_cpus10.inst 152 # number of overall hits system.cpu10.icache.overall_hits::total 153 # number of overall hits system.cpu10.icache.ReadReq_misses::cpu10.inst 2 # number of ReadReq misses system.cpu10.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu10.icache.demand_misses::cpu10.inst 2 # number of demand (read+write) misses system.cpu10.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu10.icache.overall_misses::cpu10.inst 2 # number of overall misses system.cpu10.icache.overall_misses::total 2 # number of overall misses system.cpu10.icache.ReadReq_miss_latency::cpu10.inst 164500 # number of ReadReq miss cycles system.cpu10.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu10.icache.demand_miss_latency::cpu10.inst 164500 # number of demand (read+write) miss cycles system.cpu10.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu10.icache.overall_miss_latency::cpu10.inst 164500 # number of overall miss cycles system.cpu10.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu10.icache.ReadReq_accesses::cpu10.inst 3 # number of ReadReq accesses(hits+misses) system.cpu10.icache.ReadReq_accesses::switch_cpus10.inst 152 # number of ReadReq accesses(hits+misses) system.cpu10.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu10.icache.demand_accesses::cpu10.inst 3 # number of demand (read+write) accesses system.cpu10.icache.demand_accesses::switch_cpus10.inst 152 # number of demand (read+write) accesses system.cpu10.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu10.icache.overall_accesses::cpu10.inst 3 # number of overall (read+write) accesses system.cpu10.icache.overall_accesses::switch_cpus10.inst 152 # number of overall (read+write) accesses system.cpu10.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu10.icache.ReadReq_miss_rate::cpu10.inst 0.666667 # miss rate for ReadReq accesses system.cpu10.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu10.icache.demand_miss_rate::cpu10.inst 0.666667 # miss rate for demand accesses system.cpu10.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu10.icache.overall_miss_rate::cpu10.inst 0.666667 # miss rate for overall accesses system.cpu10.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu10.icache.ReadReq_avg_miss_latency::cpu10.inst 82250 # average ReadReq miss latency system.cpu10.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu10.icache.demand_avg_miss_latency::cpu10.inst 82250 # average overall miss latency system.cpu10.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu10.icache.overall_avg_miss_latency::cpu10.inst 82250 # average overall miss latency system.cpu10.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu10.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu10.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu10.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu10.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu10.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu10.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu10.icache.ReadReq_mshr_misses::cpu10.inst 2 # number of ReadReq MSHR misses system.cpu10.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu10.icache.demand_mshr_misses::cpu10.inst 2 # number of demand (read+write) MSHR misses system.cpu10.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu10.icache.overall_mshr_misses::cpu10.inst 2 # number of overall MSHR misses system.cpu10.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu10.icache.ReadReq_mshr_miss_latency::cpu10.inst 162500 # number of ReadReq MSHR miss cycles system.cpu10.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu10.icache.demand_mshr_miss_latency::cpu10.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu10.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu10.icache.overall_mshr_miss_latency::cpu10.inst 162500 # number of overall MSHR miss cycles system.cpu10.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu10.icache.ReadReq_mshr_miss_rate::cpu10.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu10.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu10.icache.demand_mshr_miss_rate::cpu10.inst 0.666667 # mshr miss rate for demand accesses system.cpu10.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu10.icache.overall_mshr_miss_rate::cpu10.inst 0.666667 # mshr miss rate for overall accesses system.cpu10.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu10.icache.ReadReq_avg_mshr_miss_latency::cpu10.inst 81250 # average ReadReq mshr miss latency system.cpu10.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu10.icache.demand_avg_mshr_miss_latency::cpu10.inst 81250 # average overall mshr miss latency system.cpu10.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu10.icache.overall_avg_mshr_miss_latency::cpu10.inst 81250 # average overall mshr miss latency system.cpu10.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu11.branchPred.lookups 5 # Number of BP lookups system.cpu11.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu11.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu11.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu11.branchPred.BTBHits 0 # Number of BTB hits system.cpu11.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu11.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu11.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu11.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu11.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu11.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu11.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu11.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu11.dtb.fetch_hits 0 # ITB hits system.cpu11.dtb.fetch_misses 0 # ITB misses system.cpu11.dtb.fetch_acv 0 # ITB acv system.cpu11.dtb.fetch_accesses 0 # ITB accesses system.cpu11.dtb.read_hits 2 # DTB read hits system.cpu11.dtb.read_misses 0 # DTB read misses system.cpu11.dtb.read_acv 0 # DTB read access violations system.cpu11.dtb.read_accesses 0 # DTB read accesses system.cpu11.dtb.write_hits 0 # DTB write hits system.cpu11.dtb.write_misses 0 # DTB write misses system.cpu11.dtb.write_acv 0 # DTB write access violations system.cpu11.dtb.write_accesses 0 # DTB write accesses system.cpu11.dtb.data_hits 2 # DTB hits system.cpu11.dtb.data_misses 0 # DTB misses system.cpu11.dtb.data_acv 0 # DTB access violations system.cpu11.dtb.data_accesses 0 # DTB accesses system.cpu11.itb.fetch_hits 0 # ITB hits system.cpu11.itb.fetch_misses 1 # ITB misses system.cpu11.itb.fetch_acv 0 # ITB acv system.cpu11.itb.fetch_accesses 1 # ITB accesses system.cpu11.itb.read_hits 0 # DTB read hits system.cpu11.itb.read_misses 0 # DTB read misses system.cpu11.itb.read_acv 0 # DTB read access violations system.cpu11.itb.read_accesses 0 # DTB read accesses system.cpu11.itb.write_hits 0 # DTB write hits system.cpu11.itb.write_misses 0 # DTB write misses system.cpu11.itb.write_acv 0 # DTB write access violations system.cpu11.itb.write_accesses 0 # DTB write accesses system.cpu11.itb.data_hits 0 # DTB hits system.cpu11.itb.data_misses 0 # DTB misses system.cpu11.itb.data_acv 0 # DTB access violations system.cpu11.itb.data_accesses 0 # DTB accesses system.cpu11.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu11.numCycles 581 # number of cpu cycles simulated system.cpu11.numWorkItemsStarted 0 # number of work items this cpu started system.cpu11.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu11.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu11.fetch.Insts 10 # Number of instructions fetch has processed system.cpu11.fetch.Branches 5 # Number of branches that fetch encountered system.cpu11.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu11.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu11.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu11.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu11.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu11.fetch.CacheLines 3 # Number of cache lines fetched system.cpu11.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu11.fetch.branchRate 0.008606 # Number of branch fetches per cycle system.cpu11.fetch.rate 0.017212 # Number of inst fetches per cycle system.cpu11.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu11.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu11.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu11.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu11.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu11.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu11.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu11.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu11.rename.RunCycles 0 # Number of cycles rename is running system.cpu11.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu11.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu11.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu11.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu11.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu11.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu11.rename.serializingInsts 0 # count of serializing insts renamed system.cpu11.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu11.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu11.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu11.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu11.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu11.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu11.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu11.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu11.iq.iqInstsIssued 6 # Number of instructions issued system.cpu11.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu11.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu11.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu11.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu11.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu11.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu11.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu11.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu11.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu11.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu11.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu11.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu11.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu11.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu11.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu11.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu11.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu11.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu11.iq.FU_type_0::total 6 # Type of FU issued system.cpu11.iq.rate 0.010327 # Inst issue rate system.cpu11.iq.fu_busy_cnt 0 # FU busy when requested system.cpu11.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu11.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu11.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu11.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu11.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu11.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu11.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu11.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu11.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu11.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu11.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu11.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu11.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu11.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu11.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu11.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu11.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu11.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu11.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu11.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu11.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu11.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu11.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu11.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu11.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu11.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu11.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu11.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu11.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu11.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu11.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu11.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu11.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu11.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu11.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu11.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu11.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu11.iew.exec_swp 0 # number of swp insts executed system.cpu11.iew.exec_nop 1 # number of nop insts executed system.cpu11.iew.exec_refs 2 # number of memory reference insts executed system.cpu11.iew.exec_branches 1 # Number of branches executed system.cpu11.iew.exec_stores 0 # Number of stores executed system.cpu11.iew.exec_rate 0.010327 # Inst execution rate system.cpu11.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu11.iew.wb_count 5 # cumulative count of insts written-back system.cpu11.iew.wb_producers 1 # num instructions producing a value system.cpu11.iew.wb_consumers 1 # num instructions consuming a value system.cpu11.iew.wb_rate 0.008606 # insts written-back per cycle system.cpu11.iew.wb_fanout 1 # average fanout of values written-back system.cpu11.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu11.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu11.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu11.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu11.commit.committedInsts 1 # Number of instructions committed system.cpu11.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu11.commit.swp_count 0 # Number of s/w prefetches committed system.cpu11.commit.refs 1 # Number of memory references committed system.cpu11.commit.loads 1 # Number of loads committed system.cpu11.commit.membars 0 # Number of memory barriers committed system.cpu11.commit.branches 0 # Number of branches committed system.cpu11.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu11.commit.int_insts 1 # Number of committed integer instructions. system.cpu11.commit.function_calls 0 # Number of function calls committed. system.cpu11.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu11.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu11.commit.op_class_0::total 1 # Class of committed instruction system.cpu11.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu11.rob.rob_reads 60 # The number of ROB reads system.cpu11.rob.rob_writes 26 # The number of ROB writes system.cpu11.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu11.idleCycles 527 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu11.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu11.committedInsts 1 # Number of Instructions Simulated system.cpu11.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu11.cpi 581.000000 # CPI: Cycles Per Instruction system.cpu11.cpi_total 581.000000 # CPI: Total CPI of All Threads system.cpu11.ipc 0.001721 # IPC: Instructions Per Cycle system.cpu11.ipc_total 0.001721 # IPC: Total IPC of All Threads system.cpu11.int_regfile_reads 48 # number of integer regfile reads system.cpu11.int_regfile_writes 4 # number of integer regfile writes system.cpu11.fp_regfile_reads 32 # number of floating regfile reads system.cpu11.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu11.dcache.tags.replacements 0 # number of replacements system.cpu11.dcache.tags.tagsinuse 1.995824 # Cycle average of tags in use system.cpu11.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu11.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu11.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu11.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu11.dcache.tags.occ_blocks::cpu11.data 1.995824 # Average occupied blocks per requestor system.cpu11.dcache.tags.occ_percent::cpu11.data 0.003898 # Average percentage of cache occupancy system.cpu11.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu11.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu11.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu11.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu11.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu11.dcache.tags.data_accesses 210 # Number of data accesses system.cpu11.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu11.dcache.ReadReq_hits::switch_cpus11.data 50 # number of ReadReq hits system.cpu11.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu11.dcache.demand_hits::switch_cpus11.data 50 # number of demand (read+write) hits system.cpu11.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu11.dcache.overall_hits::switch_cpus11.data 50 # number of overall hits system.cpu11.dcache.overall_hits::total 50 # number of overall hits system.cpu11.dcache.ReadReq_misses::cpu11.data 2 # number of ReadReq misses system.cpu11.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu11.dcache.demand_misses::cpu11.data 2 # number of demand (read+write) misses system.cpu11.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu11.dcache.overall_misses::cpu11.data 2 # number of overall misses system.cpu11.dcache.overall_misses::total 2 # number of overall misses system.cpu11.dcache.ReadReq_miss_latency::cpu11.data 349500 # number of ReadReq miss cycles system.cpu11.dcache.ReadReq_miss_latency::total 349500 # number of ReadReq miss cycles system.cpu11.dcache.demand_miss_latency::cpu11.data 349500 # number of demand (read+write) miss cycles system.cpu11.dcache.demand_miss_latency::total 349500 # number of demand (read+write) miss cycles system.cpu11.dcache.overall_miss_latency::cpu11.data 349500 # number of overall miss cycles system.cpu11.dcache.overall_miss_latency::total 349500 # number of overall miss cycles system.cpu11.dcache.ReadReq_accesses::cpu11.data 2 # number of ReadReq accesses(hits+misses) system.cpu11.dcache.ReadReq_accesses::switch_cpus11.data 50 # number of ReadReq accesses(hits+misses) system.cpu11.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu11.dcache.demand_accesses::cpu11.data 2 # number of demand (read+write) accesses system.cpu11.dcache.demand_accesses::switch_cpus11.data 50 # number of demand (read+write) accesses system.cpu11.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu11.dcache.overall_accesses::cpu11.data 2 # number of overall (read+write) accesses system.cpu11.dcache.overall_accesses::switch_cpus11.data 50 # number of overall (read+write) accesses system.cpu11.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu11.dcache.ReadReq_miss_rate::cpu11.data 1 # miss rate for ReadReq accesses system.cpu11.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu11.dcache.demand_miss_rate::cpu11.data 1 # miss rate for demand accesses system.cpu11.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu11.dcache.overall_miss_rate::cpu11.data 1 # miss rate for overall accesses system.cpu11.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu11.dcache.ReadReq_avg_miss_latency::cpu11.data 174750 # average ReadReq miss latency system.cpu11.dcache.ReadReq_avg_miss_latency::total 174750 # average ReadReq miss latency system.cpu11.dcache.demand_avg_miss_latency::cpu11.data 174750 # average overall miss latency system.cpu11.dcache.demand_avg_miss_latency::total 174750 # average overall miss latency system.cpu11.dcache.overall_avg_miss_latency::cpu11.data 174750 # average overall miss latency system.cpu11.dcache.overall_avg_miss_latency::total 174750 # average overall miss latency system.cpu11.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu11.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu11.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu11.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu11.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu11.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu11.dcache.ReadReq_mshr_misses::cpu11.data 2 # number of ReadReq MSHR misses system.cpu11.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu11.dcache.demand_mshr_misses::cpu11.data 2 # number of demand (read+write) MSHR misses system.cpu11.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu11.dcache.overall_mshr_misses::cpu11.data 2 # number of overall MSHR misses system.cpu11.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu11.dcache.ReadReq_mshr_miss_latency::cpu11.data 347500 # number of ReadReq MSHR miss cycles system.cpu11.dcache.ReadReq_mshr_miss_latency::total 347500 # number of ReadReq MSHR miss cycles system.cpu11.dcache.demand_mshr_miss_latency::cpu11.data 347500 # number of demand (read+write) MSHR miss cycles system.cpu11.dcache.demand_mshr_miss_latency::total 347500 # number of demand (read+write) MSHR miss cycles system.cpu11.dcache.overall_mshr_miss_latency::cpu11.data 347500 # number of overall MSHR miss cycles system.cpu11.dcache.overall_mshr_miss_latency::total 347500 # number of overall MSHR miss cycles system.cpu11.dcache.ReadReq_mshr_miss_rate::cpu11.data 1 # mshr miss rate for ReadReq accesses system.cpu11.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu11.dcache.demand_mshr_miss_rate::cpu11.data 1 # mshr miss rate for demand accesses system.cpu11.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu11.dcache.overall_mshr_miss_rate::cpu11.data 1 # mshr miss rate for overall accesses system.cpu11.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu11.dcache.ReadReq_avg_mshr_miss_latency::cpu11.data 173750 # average ReadReq mshr miss latency system.cpu11.dcache.ReadReq_avg_mshr_miss_latency::total 173750 # average ReadReq mshr miss latency system.cpu11.dcache.demand_avg_mshr_miss_latency::cpu11.data 173750 # average overall mshr miss latency system.cpu11.dcache.demand_avg_mshr_miss_latency::total 173750 # average overall mshr miss latency system.cpu11.dcache.overall_avg_mshr_miss_latency::cpu11.data 173750 # average overall mshr miss latency system.cpu11.dcache.overall_avg_mshr_miss_latency::total 173750 # average overall mshr miss latency system.cpu11.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu11.icache.tags.replacements 0 # number of replacements system.cpu11.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu11.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu11.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu11.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu11.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu11.icache.tags.occ_blocks::cpu11.inst 1.995860 # Average occupied blocks per requestor system.cpu11.icache.tags.occ_percent::cpu11.inst 0.003898 # Average percentage of cache occupancy system.cpu11.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu11.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu11.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu11.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu11.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu11.icache.tags.data_accesses 622 # Number of data accesses system.cpu11.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu11.icache.ReadReq_hits::cpu11.inst 1 # number of ReadReq hits system.cpu11.icache.ReadReq_hits::switch_cpus11.inst 152 # number of ReadReq hits system.cpu11.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu11.icache.demand_hits::cpu11.inst 1 # number of demand (read+write) hits system.cpu11.icache.demand_hits::switch_cpus11.inst 152 # number of demand (read+write) hits system.cpu11.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu11.icache.overall_hits::cpu11.inst 1 # number of overall hits system.cpu11.icache.overall_hits::switch_cpus11.inst 152 # number of overall hits system.cpu11.icache.overall_hits::total 153 # number of overall hits system.cpu11.icache.ReadReq_misses::cpu11.inst 2 # number of ReadReq misses system.cpu11.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu11.icache.demand_misses::cpu11.inst 2 # number of demand (read+write) misses system.cpu11.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu11.icache.overall_misses::cpu11.inst 2 # number of overall misses system.cpu11.icache.overall_misses::total 2 # number of overall misses system.cpu11.icache.ReadReq_miss_latency::cpu11.inst 164500 # number of ReadReq miss cycles system.cpu11.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu11.icache.demand_miss_latency::cpu11.inst 164500 # number of demand (read+write) miss cycles system.cpu11.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu11.icache.overall_miss_latency::cpu11.inst 164500 # number of overall miss cycles system.cpu11.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu11.icache.ReadReq_accesses::cpu11.inst 3 # number of ReadReq accesses(hits+misses) system.cpu11.icache.ReadReq_accesses::switch_cpus11.inst 152 # number of ReadReq accesses(hits+misses) system.cpu11.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu11.icache.demand_accesses::cpu11.inst 3 # number of demand (read+write) accesses system.cpu11.icache.demand_accesses::switch_cpus11.inst 152 # number of demand (read+write) accesses system.cpu11.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu11.icache.overall_accesses::cpu11.inst 3 # number of overall (read+write) accesses system.cpu11.icache.overall_accesses::switch_cpus11.inst 152 # number of overall (read+write) accesses system.cpu11.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu11.icache.ReadReq_miss_rate::cpu11.inst 0.666667 # miss rate for ReadReq accesses system.cpu11.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu11.icache.demand_miss_rate::cpu11.inst 0.666667 # miss rate for demand accesses system.cpu11.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu11.icache.overall_miss_rate::cpu11.inst 0.666667 # miss rate for overall accesses system.cpu11.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu11.icache.ReadReq_avg_miss_latency::cpu11.inst 82250 # average ReadReq miss latency system.cpu11.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu11.icache.demand_avg_miss_latency::cpu11.inst 82250 # average overall miss latency system.cpu11.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu11.icache.overall_avg_miss_latency::cpu11.inst 82250 # average overall miss latency system.cpu11.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu11.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu11.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu11.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu11.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu11.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu11.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu11.icache.ReadReq_mshr_misses::cpu11.inst 2 # number of ReadReq MSHR misses system.cpu11.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu11.icache.demand_mshr_misses::cpu11.inst 2 # number of demand (read+write) MSHR misses system.cpu11.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu11.icache.overall_mshr_misses::cpu11.inst 2 # number of overall MSHR misses system.cpu11.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu11.icache.ReadReq_mshr_miss_latency::cpu11.inst 162500 # number of ReadReq MSHR miss cycles system.cpu11.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu11.icache.demand_mshr_miss_latency::cpu11.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu11.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu11.icache.overall_mshr_miss_latency::cpu11.inst 162500 # number of overall MSHR miss cycles system.cpu11.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu11.icache.ReadReq_mshr_miss_rate::cpu11.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu11.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu11.icache.demand_mshr_miss_rate::cpu11.inst 0.666667 # mshr miss rate for demand accesses system.cpu11.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu11.icache.overall_mshr_miss_rate::cpu11.inst 0.666667 # mshr miss rate for overall accesses system.cpu11.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu11.icache.ReadReq_avg_mshr_miss_latency::cpu11.inst 81250 # average ReadReq mshr miss latency system.cpu11.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu11.icache.demand_avg_mshr_miss_latency::cpu11.inst 81250 # average overall mshr miss latency system.cpu11.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu11.icache.overall_avg_mshr_miss_latency::cpu11.inst 81250 # average overall mshr miss latency system.cpu11.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu12.branchPred.lookups 5 # Number of BP lookups system.cpu12.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu12.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu12.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu12.branchPred.BTBHits 0 # Number of BTB hits system.cpu12.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu12.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu12.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu12.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu12.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu12.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu12.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu12.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu12.dtb.fetch_hits 0 # ITB hits system.cpu12.dtb.fetch_misses 0 # ITB misses system.cpu12.dtb.fetch_acv 0 # ITB acv system.cpu12.dtb.fetch_accesses 0 # ITB accesses system.cpu12.dtb.read_hits 2 # DTB read hits system.cpu12.dtb.read_misses 0 # DTB read misses system.cpu12.dtb.read_acv 0 # DTB read access violations system.cpu12.dtb.read_accesses 0 # DTB read accesses system.cpu12.dtb.write_hits 0 # DTB write hits system.cpu12.dtb.write_misses 0 # DTB write misses system.cpu12.dtb.write_acv 0 # DTB write access violations system.cpu12.dtb.write_accesses 0 # DTB write accesses system.cpu12.dtb.data_hits 2 # DTB hits system.cpu12.dtb.data_misses 0 # DTB misses system.cpu12.dtb.data_acv 0 # DTB access violations system.cpu12.dtb.data_accesses 0 # DTB accesses system.cpu12.itb.fetch_hits 0 # ITB hits system.cpu12.itb.fetch_misses 1 # ITB misses system.cpu12.itb.fetch_acv 0 # ITB acv system.cpu12.itb.fetch_accesses 1 # ITB accesses system.cpu12.itb.read_hits 0 # DTB read hits system.cpu12.itb.read_misses 0 # DTB read misses system.cpu12.itb.read_acv 0 # DTB read access violations system.cpu12.itb.read_accesses 0 # DTB read accesses system.cpu12.itb.write_hits 0 # DTB write hits system.cpu12.itb.write_misses 0 # DTB write misses system.cpu12.itb.write_acv 0 # DTB write access violations system.cpu12.itb.write_accesses 0 # DTB write accesses system.cpu12.itb.data_hits 0 # DTB hits system.cpu12.itb.data_misses 0 # DTB misses system.cpu12.itb.data_acv 0 # DTB access violations system.cpu12.itb.data_accesses 0 # DTB accesses system.cpu12.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu12.numCycles 591 # number of cpu cycles simulated system.cpu12.numWorkItemsStarted 0 # number of work items this cpu started system.cpu12.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu12.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu12.fetch.Insts 10 # Number of instructions fetch has processed system.cpu12.fetch.Branches 5 # Number of branches that fetch encountered system.cpu12.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu12.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu12.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu12.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu12.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu12.fetch.CacheLines 3 # Number of cache lines fetched system.cpu12.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu12.fetch.branchRate 0.008460 # Number of branch fetches per cycle system.cpu12.fetch.rate 0.016920 # Number of inst fetches per cycle system.cpu12.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu12.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu12.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu12.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu12.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu12.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu12.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu12.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu12.rename.RunCycles 0 # Number of cycles rename is running system.cpu12.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu12.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu12.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu12.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu12.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu12.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu12.rename.serializingInsts 0 # count of serializing insts renamed system.cpu12.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu12.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu12.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu12.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu12.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu12.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu12.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu12.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu12.iq.iqInstsIssued 6 # Number of instructions issued system.cpu12.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu12.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu12.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu12.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu12.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu12.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu12.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu12.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu12.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu12.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu12.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu12.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu12.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu12.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu12.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu12.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu12.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu12.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu12.iq.FU_type_0::total 6 # Type of FU issued system.cpu12.iq.rate 0.010152 # Inst issue rate system.cpu12.iq.fu_busy_cnt 0 # FU busy when requested system.cpu12.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu12.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu12.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu12.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu12.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu12.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu12.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu12.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu12.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu12.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu12.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu12.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu12.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu12.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu12.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu12.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu12.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu12.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu12.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu12.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu12.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu12.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu12.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu12.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu12.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu12.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu12.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu12.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu12.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu12.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu12.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu12.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu12.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu12.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu12.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu12.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu12.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu12.iew.exec_swp 0 # number of swp insts executed system.cpu12.iew.exec_nop 1 # number of nop insts executed system.cpu12.iew.exec_refs 2 # number of memory reference insts executed system.cpu12.iew.exec_branches 1 # Number of branches executed system.cpu12.iew.exec_stores 0 # Number of stores executed system.cpu12.iew.exec_rate 0.010152 # Inst execution rate system.cpu12.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu12.iew.wb_count 5 # cumulative count of insts written-back system.cpu12.iew.wb_producers 1 # num instructions producing a value system.cpu12.iew.wb_consumers 1 # num instructions consuming a value system.cpu12.iew.wb_rate 0.008460 # insts written-back per cycle system.cpu12.iew.wb_fanout 1 # average fanout of values written-back system.cpu12.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu12.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu12.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu12.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu12.commit.committedInsts 1 # Number of instructions committed system.cpu12.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu12.commit.swp_count 0 # Number of s/w prefetches committed system.cpu12.commit.refs 1 # Number of memory references committed system.cpu12.commit.loads 1 # Number of loads committed system.cpu12.commit.membars 0 # Number of memory barriers committed system.cpu12.commit.branches 0 # Number of branches committed system.cpu12.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu12.commit.int_insts 1 # Number of committed integer instructions. system.cpu12.commit.function_calls 0 # Number of function calls committed. system.cpu12.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu12.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu12.commit.op_class_0::total 1 # Class of committed instruction system.cpu12.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu12.rob.rob_reads 60 # The number of ROB reads system.cpu12.rob.rob_writes 26 # The number of ROB writes system.cpu12.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu12.idleCycles 537 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu12.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu12.committedInsts 1 # Number of Instructions Simulated system.cpu12.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu12.cpi 591.000000 # CPI: Cycles Per Instruction system.cpu12.cpi_total 591.000000 # CPI: Total CPI of All Threads system.cpu12.ipc 0.001692 # IPC: Instructions Per Cycle system.cpu12.ipc_total 0.001692 # IPC: Total IPC of All Threads system.cpu12.int_regfile_reads 48 # number of integer regfile reads system.cpu12.int_regfile_writes 4 # number of integer regfile writes system.cpu12.fp_regfile_reads 32 # number of floating regfile reads system.cpu12.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu12.dcache.tags.replacements 0 # number of replacements system.cpu12.dcache.tags.tagsinuse 1.995824 # Cycle average of tags in use system.cpu12.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu12.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu12.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu12.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu12.dcache.tags.occ_blocks::cpu12.data 1.995824 # Average occupied blocks per requestor system.cpu12.dcache.tags.occ_percent::cpu12.data 0.003898 # Average percentage of cache occupancy system.cpu12.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu12.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu12.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu12.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu12.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu12.dcache.tags.data_accesses 210 # Number of data accesses system.cpu12.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu12.dcache.ReadReq_hits::switch_cpus12.data 50 # number of ReadReq hits system.cpu12.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu12.dcache.demand_hits::switch_cpus12.data 50 # number of demand (read+write) hits system.cpu12.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu12.dcache.overall_hits::switch_cpus12.data 50 # number of overall hits system.cpu12.dcache.overall_hits::total 50 # number of overall hits system.cpu12.dcache.ReadReq_misses::cpu12.data 2 # number of ReadReq misses system.cpu12.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu12.dcache.demand_misses::cpu12.data 2 # number of demand (read+write) misses system.cpu12.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu12.dcache.overall_misses::cpu12.data 2 # number of overall misses system.cpu12.dcache.overall_misses::total 2 # number of overall misses system.cpu12.dcache.ReadReq_miss_latency::cpu12.data 354500 # number of ReadReq miss cycles system.cpu12.dcache.ReadReq_miss_latency::total 354500 # number of ReadReq miss cycles system.cpu12.dcache.demand_miss_latency::cpu12.data 354500 # number of demand (read+write) miss cycles system.cpu12.dcache.demand_miss_latency::total 354500 # number of demand (read+write) miss cycles system.cpu12.dcache.overall_miss_latency::cpu12.data 354500 # number of overall miss cycles system.cpu12.dcache.overall_miss_latency::total 354500 # number of overall miss cycles system.cpu12.dcache.ReadReq_accesses::cpu12.data 2 # number of ReadReq accesses(hits+misses) system.cpu12.dcache.ReadReq_accesses::switch_cpus12.data 50 # number of ReadReq accesses(hits+misses) system.cpu12.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu12.dcache.demand_accesses::cpu12.data 2 # number of demand (read+write) accesses system.cpu12.dcache.demand_accesses::switch_cpus12.data 50 # number of demand (read+write) accesses system.cpu12.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu12.dcache.overall_accesses::cpu12.data 2 # number of overall (read+write) accesses system.cpu12.dcache.overall_accesses::switch_cpus12.data 50 # number of overall (read+write) accesses system.cpu12.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu12.dcache.ReadReq_miss_rate::cpu12.data 1 # miss rate for ReadReq accesses system.cpu12.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu12.dcache.demand_miss_rate::cpu12.data 1 # miss rate for demand accesses system.cpu12.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu12.dcache.overall_miss_rate::cpu12.data 1 # miss rate for overall accesses system.cpu12.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu12.dcache.ReadReq_avg_miss_latency::cpu12.data 177250 # average ReadReq miss latency system.cpu12.dcache.ReadReq_avg_miss_latency::total 177250 # average ReadReq miss latency system.cpu12.dcache.demand_avg_miss_latency::cpu12.data 177250 # average overall miss latency system.cpu12.dcache.demand_avg_miss_latency::total 177250 # average overall miss latency system.cpu12.dcache.overall_avg_miss_latency::cpu12.data 177250 # average overall miss latency system.cpu12.dcache.overall_avg_miss_latency::total 177250 # average overall miss latency system.cpu12.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu12.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu12.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu12.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu12.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu12.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu12.dcache.ReadReq_mshr_misses::cpu12.data 2 # number of ReadReq MSHR misses system.cpu12.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu12.dcache.demand_mshr_misses::cpu12.data 2 # number of demand (read+write) MSHR misses system.cpu12.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu12.dcache.overall_mshr_misses::cpu12.data 2 # number of overall MSHR misses system.cpu12.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu12.dcache.ReadReq_mshr_miss_latency::cpu12.data 352500 # number of ReadReq MSHR miss cycles system.cpu12.dcache.ReadReq_mshr_miss_latency::total 352500 # number of ReadReq MSHR miss cycles system.cpu12.dcache.demand_mshr_miss_latency::cpu12.data 352500 # number of demand (read+write) MSHR miss cycles system.cpu12.dcache.demand_mshr_miss_latency::total 352500 # number of demand (read+write) MSHR miss cycles system.cpu12.dcache.overall_mshr_miss_latency::cpu12.data 352500 # number of overall MSHR miss cycles system.cpu12.dcache.overall_mshr_miss_latency::total 352500 # number of overall MSHR miss cycles system.cpu12.dcache.ReadReq_mshr_miss_rate::cpu12.data 1 # mshr miss rate for ReadReq accesses system.cpu12.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu12.dcache.demand_mshr_miss_rate::cpu12.data 1 # mshr miss rate for demand accesses system.cpu12.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu12.dcache.overall_mshr_miss_rate::cpu12.data 1 # mshr miss rate for overall accesses system.cpu12.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu12.dcache.ReadReq_avg_mshr_miss_latency::cpu12.data 176250 # average ReadReq mshr miss latency system.cpu12.dcache.ReadReq_avg_mshr_miss_latency::total 176250 # average ReadReq mshr miss latency system.cpu12.dcache.demand_avg_mshr_miss_latency::cpu12.data 176250 # average overall mshr miss latency system.cpu12.dcache.demand_avg_mshr_miss_latency::total 176250 # average overall mshr miss latency system.cpu12.dcache.overall_avg_mshr_miss_latency::cpu12.data 176250 # average overall mshr miss latency system.cpu12.dcache.overall_avg_mshr_miss_latency::total 176250 # average overall mshr miss latency system.cpu12.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu12.icache.tags.replacements 0 # number of replacements system.cpu12.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu12.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu12.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu12.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu12.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu12.icache.tags.occ_blocks::cpu12.inst 1.995860 # Average occupied blocks per requestor system.cpu12.icache.tags.occ_percent::cpu12.inst 0.003898 # Average percentage of cache occupancy system.cpu12.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu12.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu12.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu12.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu12.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu12.icache.tags.data_accesses 622 # Number of data accesses system.cpu12.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu12.icache.ReadReq_hits::cpu12.inst 1 # number of ReadReq hits system.cpu12.icache.ReadReq_hits::switch_cpus12.inst 152 # number of ReadReq hits system.cpu12.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu12.icache.demand_hits::cpu12.inst 1 # number of demand (read+write) hits system.cpu12.icache.demand_hits::switch_cpus12.inst 152 # number of demand (read+write) hits system.cpu12.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu12.icache.overall_hits::cpu12.inst 1 # number of overall hits system.cpu12.icache.overall_hits::switch_cpus12.inst 152 # number of overall hits system.cpu12.icache.overall_hits::total 153 # number of overall hits system.cpu12.icache.ReadReq_misses::cpu12.inst 2 # number of ReadReq misses system.cpu12.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu12.icache.demand_misses::cpu12.inst 2 # number of demand (read+write) misses system.cpu12.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu12.icache.overall_misses::cpu12.inst 2 # number of overall misses system.cpu12.icache.overall_misses::total 2 # number of overall misses system.cpu12.icache.ReadReq_miss_latency::cpu12.inst 164500 # number of ReadReq miss cycles system.cpu12.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu12.icache.demand_miss_latency::cpu12.inst 164500 # number of demand (read+write) miss cycles system.cpu12.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu12.icache.overall_miss_latency::cpu12.inst 164500 # number of overall miss cycles system.cpu12.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu12.icache.ReadReq_accesses::cpu12.inst 3 # number of ReadReq accesses(hits+misses) system.cpu12.icache.ReadReq_accesses::switch_cpus12.inst 152 # number of ReadReq accesses(hits+misses) system.cpu12.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu12.icache.demand_accesses::cpu12.inst 3 # number of demand (read+write) accesses system.cpu12.icache.demand_accesses::switch_cpus12.inst 152 # number of demand (read+write) accesses system.cpu12.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu12.icache.overall_accesses::cpu12.inst 3 # number of overall (read+write) accesses system.cpu12.icache.overall_accesses::switch_cpus12.inst 152 # number of overall (read+write) accesses system.cpu12.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu12.icache.ReadReq_miss_rate::cpu12.inst 0.666667 # miss rate for ReadReq accesses system.cpu12.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu12.icache.demand_miss_rate::cpu12.inst 0.666667 # miss rate for demand accesses system.cpu12.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu12.icache.overall_miss_rate::cpu12.inst 0.666667 # miss rate for overall accesses system.cpu12.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu12.icache.ReadReq_avg_miss_latency::cpu12.inst 82250 # average ReadReq miss latency system.cpu12.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu12.icache.demand_avg_miss_latency::cpu12.inst 82250 # average overall miss latency system.cpu12.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu12.icache.overall_avg_miss_latency::cpu12.inst 82250 # average overall miss latency system.cpu12.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu12.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu12.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu12.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu12.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu12.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu12.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu12.icache.ReadReq_mshr_misses::cpu12.inst 2 # number of ReadReq MSHR misses system.cpu12.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu12.icache.demand_mshr_misses::cpu12.inst 2 # number of demand (read+write) MSHR misses system.cpu12.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu12.icache.overall_mshr_misses::cpu12.inst 2 # number of overall MSHR misses system.cpu12.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu12.icache.ReadReq_mshr_miss_latency::cpu12.inst 162500 # number of ReadReq MSHR miss cycles system.cpu12.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu12.icache.demand_mshr_miss_latency::cpu12.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu12.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu12.icache.overall_mshr_miss_latency::cpu12.inst 162500 # number of overall MSHR miss cycles system.cpu12.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu12.icache.ReadReq_mshr_miss_rate::cpu12.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu12.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu12.icache.demand_mshr_miss_rate::cpu12.inst 0.666667 # mshr miss rate for demand accesses system.cpu12.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu12.icache.overall_mshr_miss_rate::cpu12.inst 0.666667 # mshr miss rate for overall accesses system.cpu12.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu12.icache.ReadReq_avg_mshr_miss_latency::cpu12.inst 81250 # average ReadReq mshr miss latency system.cpu12.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu12.icache.demand_avg_mshr_miss_latency::cpu12.inst 81250 # average overall mshr miss latency system.cpu12.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu12.icache.overall_avg_mshr_miss_latency::cpu12.inst 81250 # average overall mshr miss latency system.cpu12.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu13.branchPred.lookups 5 # Number of BP lookups system.cpu13.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu13.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu13.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu13.branchPred.BTBHits 0 # Number of BTB hits system.cpu13.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu13.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu13.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu13.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu13.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu13.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu13.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu13.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu13.dtb.fetch_hits 0 # ITB hits system.cpu13.dtb.fetch_misses 0 # ITB misses system.cpu13.dtb.fetch_acv 0 # ITB acv system.cpu13.dtb.fetch_accesses 0 # ITB accesses system.cpu13.dtb.read_hits 2 # DTB read hits system.cpu13.dtb.read_misses 0 # DTB read misses system.cpu13.dtb.read_acv 0 # DTB read access violations system.cpu13.dtb.read_accesses 0 # DTB read accesses system.cpu13.dtb.write_hits 0 # DTB write hits system.cpu13.dtb.write_misses 0 # DTB write misses system.cpu13.dtb.write_acv 0 # DTB write access violations system.cpu13.dtb.write_accesses 0 # DTB write accesses system.cpu13.dtb.data_hits 2 # DTB hits system.cpu13.dtb.data_misses 0 # DTB misses system.cpu13.dtb.data_acv 0 # DTB access violations system.cpu13.dtb.data_accesses 0 # DTB accesses system.cpu13.itb.fetch_hits 0 # ITB hits system.cpu13.itb.fetch_misses 1 # ITB misses system.cpu13.itb.fetch_acv 0 # ITB acv system.cpu13.itb.fetch_accesses 1 # ITB accesses system.cpu13.itb.read_hits 0 # DTB read hits system.cpu13.itb.read_misses 0 # DTB read misses system.cpu13.itb.read_acv 0 # DTB read access violations system.cpu13.itb.read_accesses 0 # DTB read accesses system.cpu13.itb.write_hits 0 # DTB write hits system.cpu13.itb.write_misses 0 # DTB write misses system.cpu13.itb.write_acv 0 # DTB write access violations system.cpu13.itb.write_accesses 0 # DTB write accesses system.cpu13.itb.data_hits 0 # DTB hits system.cpu13.itb.data_misses 0 # DTB misses system.cpu13.itb.data_acv 0 # DTB access violations system.cpu13.itb.data_accesses 0 # DTB accesses system.cpu13.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu13.numCycles 601 # number of cpu cycles simulated system.cpu13.numWorkItemsStarted 0 # number of work items this cpu started system.cpu13.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu13.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu13.fetch.Insts 10 # Number of instructions fetch has processed system.cpu13.fetch.Branches 5 # Number of branches that fetch encountered system.cpu13.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu13.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu13.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu13.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu13.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu13.fetch.CacheLines 3 # Number of cache lines fetched system.cpu13.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu13.fetch.branchRate 0.008319 # Number of branch fetches per cycle system.cpu13.fetch.rate 0.016639 # Number of inst fetches per cycle system.cpu13.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu13.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu13.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu13.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu13.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu13.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu13.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu13.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu13.rename.RunCycles 0 # Number of cycles rename is running system.cpu13.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu13.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu13.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu13.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu13.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu13.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu13.rename.serializingInsts 0 # count of serializing insts renamed system.cpu13.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu13.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu13.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu13.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu13.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu13.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu13.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu13.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu13.iq.iqInstsIssued 6 # Number of instructions issued system.cpu13.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu13.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu13.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu13.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu13.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu13.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu13.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu13.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu13.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu13.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu13.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu13.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu13.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu13.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu13.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu13.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu13.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu13.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu13.iq.FU_type_0::total 6 # Type of FU issued system.cpu13.iq.rate 0.009983 # Inst issue rate system.cpu13.iq.fu_busy_cnt 0 # FU busy when requested system.cpu13.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu13.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu13.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu13.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu13.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu13.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu13.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu13.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu13.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu13.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu13.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu13.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu13.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu13.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu13.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu13.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu13.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu13.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu13.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu13.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu13.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu13.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu13.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu13.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu13.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu13.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu13.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu13.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu13.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu13.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu13.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu13.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu13.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu13.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu13.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu13.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu13.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu13.iew.exec_swp 0 # number of swp insts executed system.cpu13.iew.exec_nop 1 # number of nop insts executed system.cpu13.iew.exec_refs 2 # number of memory reference insts executed system.cpu13.iew.exec_branches 1 # Number of branches executed system.cpu13.iew.exec_stores 0 # Number of stores executed system.cpu13.iew.exec_rate 0.009983 # Inst execution rate system.cpu13.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu13.iew.wb_count 5 # cumulative count of insts written-back system.cpu13.iew.wb_producers 1 # num instructions producing a value system.cpu13.iew.wb_consumers 1 # num instructions consuming a value system.cpu13.iew.wb_rate 0.008319 # insts written-back per cycle system.cpu13.iew.wb_fanout 1 # average fanout of values written-back system.cpu13.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu13.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu13.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu13.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu13.commit.committedInsts 1 # Number of instructions committed system.cpu13.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu13.commit.swp_count 0 # Number of s/w prefetches committed system.cpu13.commit.refs 1 # Number of memory references committed system.cpu13.commit.loads 1 # Number of loads committed system.cpu13.commit.membars 0 # Number of memory barriers committed system.cpu13.commit.branches 0 # Number of branches committed system.cpu13.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu13.commit.int_insts 1 # Number of committed integer instructions. system.cpu13.commit.function_calls 0 # Number of function calls committed. system.cpu13.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu13.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu13.commit.op_class_0::total 1 # Class of committed instruction system.cpu13.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu13.rob.rob_reads 60 # The number of ROB reads system.cpu13.rob.rob_writes 26 # The number of ROB writes system.cpu13.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu13.idleCycles 547 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu13.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu13.committedInsts 1 # Number of Instructions Simulated system.cpu13.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu13.cpi 601.000000 # CPI: Cycles Per Instruction system.cpu13.cpi_total 601.000000 # CPI: Total CPI of All Threads system.cpu13.ipc 0.001664 # IPC: Instructions Per Cycle system.cpu13.ipc_total 0.001664 # IPC: Total IPC of All Threads system.cpu13.int_regfile_reads 48 # number of integer regfile reads system.cpu13.int_regfile_writes 4 # number of integer regfile writes system.cpu13.fp_regfile_reads 32 # number of floating regfile reads system.cpu13.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu13.dcache.tags.replacements 0 # number of replacements system.cpu13.dcache.tags.tagsinuse 1.995823 # Cycle average of tags in use system.cpu13.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu13.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu13.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu13.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu13.dcache.tags.occ_blocks::cpu13.data 1.995823 # Average occupied blocks per requestor system.cpu13.dcache.tags.occ_percent::cpu13.data 0.003898 # Average percentage of cache occupancy system.cpu13.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu13.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu13.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu13.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu13.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu13.dcache.tags.data_accesses 210 # Number of data accesses system.cpu13.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu13.dcache.ReadReq_hits::switch_cpus13.data 50 # number of ReadReq hits system.cpu13.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu13.dcache.demand_hits::switch_cpus13.data 50 # number of demand (read+write) hits system.cpu13.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu13.dcache.overall_hits::switch_cpus13.data 50 # number of overall hits system.cpu13.dcache.overall_hits::total 50 # number of overall hits system.cpu13.dcache.ReadReq_misses::cpu13.data 2 # number of ReadReq misses system.cpu13.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu13.dcache.demand_misses::cpu13.data 2 # number of demand (read+write) misses system.cpu13.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu13.dcache.overall_misses::cpu13.data 2 # number of overall misses system.cpu13.dcache.overall_misses::total 2 # number of overall misses system.cpu13.dcache.ReadReq_miss_latency::cpu13.data 359500 # number of ReadReq miss cycles system.cpu13.dcache.ReadReq_miss_latency::total 359500 # number of ReadReq miss cycles system.cpu13.dcache.demand_miss_latency::cpu13.data 359500 # number of demand (read+write) miss cycles system.cpu13.dcache.demand_miss_latency::total 359500 # number of demand (read+write) miss cycles system.cpu13.dcache.overall_miss_latency::cpu13.data 359500 # number of overall miss cycles system.cpu13.dcache.overall_miss_latency::total 359500 # number of overall miss cycles system.cpu13.dcache.ReadReq_accesses::cpu13.data 2 # number of ReadReq accesses(hits+misses) system.cpu13.dcache.ReadReq_accesses::switch_cpus13.data 50 # number of ReadReq accesses(hits+misses) system.cpu13.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu13.dcache.demand_accesses::cpu13.data 2 # number of demand (read+write) accesses system.cpu13.dcache.demand_accesses::switch_cpus13.data 50 # number of demand (read+write) accesses system.cpu13.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu13.dcache.overall_accesses::cpu13.data 2 # number of overall (read+write) accesses system.cpu13.dcache.overall_accesses::switch_cpus13.data 50 # number of overall (read+write) accesses system.cpu13.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu13.dcache.ReadReq_miss_rate::cpu13.data 1 # miss rate for ReadReq accesses system.cpu13.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu13.dcache.demand_miss_rate::cpu13.data 1 # miss rate for demand accesses system.cpu13.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu13.dcache.overall_miss_rate::cpu13.data 1 # miss rate for overall accesses system.cpu13.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu13.dcache.ReadReq_avg_miss_latency::cpu13.data 179750 # average ReadReq miss latency system.cpu13.dcache.ReadReq_avg_miss_latency::total 179750 # average ReadReq miss latency system.cpu13.dcache.demand_avg_miss_latency::cpu13.data 179750 # average overall miss latency system.cpu13.dcache.demand_avg_miss_latency::total 179750 # average overall miss latency system.cpu13.dcache.overall_avg_miss_latency::cpu13.data 179750 # average overall miss latency system.cpu13.dcache.overall_avg_miss_latency::total 179750 # average overall miss latency system.cpu13.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu13.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu13.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu13.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu13.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu13.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu13.dcache.ReadReq_mshr_misses::cpu13.data 2 # number of ReadReq MSHR misses system.cpu13.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu13.dcache.demand_mshr_misses::cpu13.data 2 # number of demand (read+write) MSHR misses system.cpu13.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu13.dcache.overall_mshr_misses::cpu13.data 2 # number of overall MSHR misses system.cpu13.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu13.dcache.ReadReq_mshr_miss_latency::cpu13.data 357500 # number of ReadReq MSHR miss cycles system.cpu13.dcache.ReadReq_mshr_miss_latency::total 357500 # number of ReadReq MSHR miss cycles system.cpu13.dcache.demand_mshr_miss_latency::cpu13.data 357500 # number of demand (read+write) MSHR miss cycles system.cpu13.dcache.demand_mshr_miss_latency::total 357500 # number of demand (read+write) MSHR miss cycles system.cpu13.dcache.overall_mshr_miss_latency::cpu13.data 357500 # number of overall MSHR miss cycles system.cpu13.dcache.overall_mshr_miss_latency::total 357500 # number of overall MSHR miss cycles system.cpu13.dcache.ReadReq_mshr_miss_rate::cpu13.data 1 # mshr miss rate for ReadReq accesses system.cpu13.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu13.dcache.demand_mshr_miss_rate::cpu13.data 1 # mshr miss rate for demand accesses system.cpu13.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu13.dcache.overall_mshr_miss_rate::cpu13.data 1 # mshr miss rate for overall accesses system.cpu13.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu13.dcache.ReadReq_avg_mshr_miss_latency::cpu13.data 178750 # average ReadReq mshr miss latency system.cpu13.dcache.ReadReq_avg_mshr_miss_latency::total 178750 # average ReadReq mshr miss latency system.cpu13.dcache.demand_avg_mshr_miss_latency::cpu13.data 178750 # average overall mshr miss latency system.cpu13.dcache.demand_avg_mshr_miss_latency::total 178750 # average overall mshr miss latency system.cpu13.dcache.overall_avg_mshr_miss_latency::cpu13.data 178750 # average overall mshr miss latency system.cpu13.dcache.overall_avg_mshr_miss_latency::total 178750 # average overall mshr miss latency system.cpu13.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu13.icache.tags.replacements 0 # number of replacements system.cpu13.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu13.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu13.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu13.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu13.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu13.icache.tags.occ_blocks::cpu13.inst 1.995860 # Average occupied blocks per requestor system.cpu13.icache.tags.occ_percent::cpu13.inst 0.003898 # Average percentage of cache occupancy system.cpu13.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu13.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu13.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu13.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu13.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu13.icache.tags.data_accesses 622 # Number of data accesses system.cpu13.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu13.icache.ReadReq_hits::cpu13.inst 1 # number of ReadReq hits system.cpu13.icache.ReadReq_hits::switch_cpus13.inst 152 # number of ReadReq hits system.cpu13.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu13.icache.demand_hits::cpu13.inst 1 # number of demand (read+write) hits system.cpu13.icache.demand_hits::switch_cpus13.inst 152 # number of demand (read+write) hits system.cpu13.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu13.icache.overall_hits::cpu13.inst 1 # number of overall hits system.cpu13.icache.overall_hits::switch_cpus13.inst 152 # number of overall hits system.cpu13.icache.overall_hits::total 153 # number of overall hits system.cpu13.icache.ReadReq_misses::cpu13.inst 2 # number of ReadReq misses system.cpu13.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu13.icache.demand_misses::cpu13.inst 2 # number of demand (read+write) misses system.cpu13.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu13.icache.overall_misses::cpu13.inst 2 # number of overall misses system.cpu13.icache.overall_misses::total 2 # number of overall misses system.cpu13.icache.ReadReq_miss_latency::cpu13.inst 164500 # number of ReadReq miss cycles system.cpu13.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu13.icache.demand_miss_latency::cpu13.inst 164500 # number of demand (read+write) miss cycles system.cpu13.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu13.icache.overall_miss_latency::cpu13.inst 164500 # number of overall miss cycles system.cpu13.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu13.icache.ReadReq_accesses::cpu13.inst 3 # number of ReadReq accesses(hits+misses) system.cpu13.icache.ReadReq_accesses::switch_cpus13.inst 152 # number of ReadReq accesses(hits+misses) system.cpu13.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu13.icache.demand_accesses::cpu13.inst 3 # number of demand (read+write) accesses system.cpu13.icache.demand_accesses::switch_cpus13.inst 152 # number of demand (read+write) accesses system.cpu13.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu13.icache.overall_accesses::cpu13.inst 3 # number of overall (read+write) accesses system.cpu13.icache.overall_accesses::switch_cpus13.inst 152 # number of overall (read+write) accesses system.cpu13.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu13.icache.ReadReq_miss_rate::cpu13.inst 0.666667 # miss rate for ReadReq accesses system.cpu13.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu13.icache.demand_miss_rate::cpu13.inst 0.666667 # miss rate for demand accesses system.cpu13.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu13.icache.overall_miss_rate::cpu13.inst 0.666667 # miss rate for overall accesses system.cpu13.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu13.icache.ReadReq_avg_miss_latency::cpu13.inst 82250 # average ReadReq miss latency system.cpu13.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu13.icache.demand_avg_miss_latency::cpu13.inst 82250 # average overall miss latency system.cpu13.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu13.icache.overall_avg_miss_latency::cpu13.inst 82250 # average overall miss latency system.cpu13.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu13.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu13.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu13.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu13.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu13.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu13.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu13.icache.ReadReq_mshr_misses::cpu13.inst 2 # number of ReadReq MSHR misses system.cpu13.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu13.icache.demand_mshr_misses::cpu13.inst 2 # number of demand (read+write) MSHR misses system.cpu13.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu13.icache.overall_mshr_misses::cpu13.inst 2 # number of overall MSHR misses system.cpu13.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu13.icache.ReadReq_mshr_miss_latency::cpu13.inst 162500 # number of ReadReq MSHR miss cycles system.cpu13.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu13.icache.demand_mshr_miss_latency::cpu13.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu13.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu13.icache.overall_mshr_miss_latency::cpu13.inst 162500 # number of overall MSHR miss cycles system.cpu13.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu13.icache.ReadReq_mshr_miss_rate::cpu13.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu13.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu13.icache.demand_mshr_miss_rate::cpu13.inst 0.666667 # mshr miss rate for demand accesses system.cpu13.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu13.icache.overall_mshr_miss_rate::cpu13.inst 0.666667 # mshr miss rate for overall accesses system.cpu13.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu13.icache.ReadReq_avg_mshr_miss_latency::cpu13.inst 81250 # average ReadReq mshr miss latency system.cpu13.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu13.icache.demand_avg_mshr_miss_latency::cpu13.inst 81250 # average overall mshr miss latency system.cpu13.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu13.icache.overall_avg_mshr_miss_latency::cpu13.inst 81250 # average overall mshr miss latency system.cpu13.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu14.branchPred.lookups 5 # Number of BP lookups system.cpu14.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu14.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu14.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu14.branchPred.BTBHits 0 # Number of BTB hits system.cpu14.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu14.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu14.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu14.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu14.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu14.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu14.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu14.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu14.dtb.fetch_hits 0 # ITB hits system.cpu14.dtb.fetch_misses 0 # ITB misses system.cpu14.dtb.fetch_acv 0 # ITB acv system.cpu14.dtb.fetch_accesses 0 # ITB accesses system.cpu14.dtb.read_hits 2 # DTB read hits system.cpu14.dtb.read_misses 0 # DTB read misses system.cpu14.dtb.read_acv 0 # DTB read access violations system.cpu14.dtb.read_accesses 0 # DTB read accesses system.cpu14.dtb.write_hits 0 # DTB write hits system.cpu14.dtb.write_misses 0 # DTB write misses system.cpu14.dtb.write_acv 0 # DTB write access violations system.cpu14.dtb.write_accesses 0 # DTB write accesses system.cpu14.dtb.data_hits 2 # DTB hits system.cpu14.dtb.data_misses 0 # DTB misses system.cpu14.dtb.data_acv 0 # DTB access violations system.cpu14.dtb.data_accesses 0 # DTB accesses system.cpu14.itb.fetch_hits 0 # ITB hits system.cpu14.itb.fetch_misses 1 # ITB misses system.cpu14.itb.fetch_acv 0 # ITB acv system.cpu14.itb.fetch_accesses 1 # ITB accesses system.cpu14.itb.read_hits 0 # DTB read hits system.cpu14.itb.read_misses 0 # DTB read misses system.cpu14.itb.read_acv 0 # DTB read access violations system.cpu14.itb.read_accesses 0 # DTB read accesses system.cpu14.itb.write_hits 0 # DTB write hits system.cpu14.itb.write_misses 0 # DTB write misses system.cpu14.itb.write_acv 0 # DTB write access violations system.cpu14.itb.write_accesses 0 # DTB write accesses system.cpu14.itb.data_hits 0 # DTB hits system.cpu14.itb.data_misses 0 # DTB misses system.cpu14.itb.data_acv 0 # DTB access violations system.cpu14.itb.data_accesses 0 # DTB accesses system.cpu14.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu14.numCycles 611 # number of cpu cycles simulated system.cpu14.numWorkItemsStarted 0 # number of work items this cpu started system.cpu14.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu14.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu14.fetch.Insts 10 # Number of instructions fetch has processed system.cpu14.fetch.Branches 5 # Number of branches that fetch encountered system.cpu14.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu14.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu14.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu14.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu14.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu14.fetch.CacheLines 3 # Number of cache lines fetched system.cpu14.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu14.fetch.branchRate 0.008183 # Number of branch fetches per cycle system.cpu14.fetch.rate 0.016367 # Number of inst fetches per cycle system.cpu14.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu14.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu14.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu14.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu14.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu14.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu14.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu14.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu14.rename.RunCycles 0 # Number of cycles rename is running system.cpu14.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu14.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu14.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu14.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu14.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu14.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu14.rename.serializingInsts 0 # count of serializing insts renamed system.cpu14.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu14.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu14.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu14.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu14.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu14.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu14.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu14.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu14.iq.iqInstsIssued 6 # Number of instructions issued system.cpu14.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu14.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu14.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu14.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu14.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu14.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu14.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu14.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu14.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu14.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu14.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu14.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu14.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu14.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu14.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu14.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu14.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu14.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu14.iq.FU_type_0::total 6 # Type of FU issued system.cpu14.iq.rate 0.009820 # Inst issue rate system.cpu14.iq.fu_busy_cnt 0 # FU busy when requested system.cpu14.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu14.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu14.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu14.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu14.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu14.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu14.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu14.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu14.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu14.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu14.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu14.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu14.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu14.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu14.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu14.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu14.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu14.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu14.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu14.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu14.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu14.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu14.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu14.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu14.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu14.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu14.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu14.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu14.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu14.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu14.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu14.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu14.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu14.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu14.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu14.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu14.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu14.iew.exec_swp 0 # number of swp insts executed system.cpu14.iew.exec_nop 1 # number of nop insts executed system.cpu14.iew.exec_refs 2 # number of memory reference insts executed system.cpu14.iew.exec_branches 1 # Number of branches executed system.cpu14.iew.exec_stores 0 # Number of stores executed system.cpu14.iew.exec_rate 0.009820 # Inst execution rate system.cpu14.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu14.iew.wb_count 5 # cumulative count of insts written-back system.cpu14.iew.wb_producers 1 # num instructions producing a value system.cpu14.iew.wb_consumers 1 # num instructions consuming a value system.cpu14.iew.wb_rate 0.008183 # insts written-back per cycle system.cpu14.iew.wb_fanout 1 # average fanout of values written-back system.cpu14.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu14.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu14.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu14.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu14.commit.committedInsts 1 # Number of instructions committed system.cpu14.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu14.commit.swp_count 0 # Number of s/w prefetches committed system.cpu14.commit.refs 1 # Number of memory references committed system.cpu14.commit.loads 1 # Number of loads committed system.cpu14.commit.membars 0 # Number of memory barriers committed system.cpu14.commit.branches 0 # Number of branches committed system.cpu14.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu14.commit.int_insts 1 # Number of committed integer instructions. system.cpu14.commit.function_calls 0 # Number of function calls committed. system.cpu14.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu14.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu14.commit.op_class_0::total 1 # Class of committed instruction system.cpu14.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu14.rob.rob_reads 60 # The number of ROB reads system.cpu14.rob.rob_writes 26 # The number of ROB writes system.cpu14.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu14.idleCycles 557 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu14.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu14.committedInsts 1 # Number of Instructions Simulated system.cpu14.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu14.cpi 611.000000 # CPI: Cycles Per Instruction system.cpu14.cpi_total 611.000000 # CPI: Total CPI of All Threads system.cpu14.ipc 0.001637 # IPC: Instructions Per Cycle system.cpu14.ipc_total 0.001637 # IPC: Total IPC of All Threads system.cpu14.int_regfile_reads 48 # number of integer regfile reads system.cpu14.int_regfile_writes 4 # number of integer regfile writes system.cpu14.fp_regfile_reads 32 # number of floating regfile reads system.cpu14.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu14.dcache.tags.replacements 0 # number of replacements system.cpu14.dcache.tags.tagsinuse 1.995823 # Cycle average of tags in use system.cpu14.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu14.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu14.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu14.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu14.dcache.tags.occ_blocks::cpu14.data 1.995823 # Average occupied blocks per requestor system.cpu14.dcache.tags.occ_percent::cpu14.data 0.003898 # Average percentage of cache occupancy system.cpu14.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu14.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu14.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu14.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu14.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu14.dcache.tags.data_accesses 210 # Number of data accesses system.cpu14.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu14.dcache.ReadReq_hits::switch_cpus14.data 50 # number of ReadReq hits system.cpu14.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu14.dcache.demand_hits::switch_cpus14.data 50 # number of demand (read+write) hits system.cpu14.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu14.dcache.overall_hits::switch_cpus14.data 50 # number of overall hits system.cpu14.dcache.overall_hits::total 50 # number of overall hits system.cpu14.dcache.ReadReq_misses::cpu14.data 2 # number of ReadReq misses system.cpu14.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu14.dcache.demand_misses::cpu14.data 2 # number of demand (read+write) misses system.cpu14.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu14.dcache.overall_misses::cpu14.data 2 # number of overall misses system.cpu14.dcache.overall_misses::total 2 # number of overall misses system.cpu14.dcache.ReadReq_miss_latency::cpu14.data 364500 # number of ReadReq miss cycles system.cpu14.dcache.ReadReq_miss_latency::total 364500 # number of ReadReq miss cycles system.cpu14.dcache.demand_miss_latency::cpu14.data 364500 # number of demand (read+write) miss cycles system.cpu14.dcache.demand_miss_latency::total 364500 # number of demand (read+write) miss cycles system.cpu14.dcache.overall_miss_latency::cpu14.data 364500 # number of overall miss cycles system.cpu14.dcache.overall_miss_latency::total 364500 # number of overall miss cycles system.cpu14.dcache.ReadReq_accesses::cpu14.data 2 # number of ReadReq accesses(hits+misses) system.cpu14.dcache.ReadReq_accesses::switch_cpus14.data 50 # number of ReadReq accesses(hits+misses) system.cpu14.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu14.dcache.demand_accesses::cpu14.data 2 # number of demand (read+write) accesses system.cpu14.dcache.demand_accesses::switch_cpus14.data 50 # number of demand (read+write) accesses system.cpu14.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu14.dcache.overall_accesses::cpu14.data 2 # number of overall (read+write) accesses system.cpu14.dcache.overall_accesses::switch_cpus14.data 50 # number of overall (read+write) accesses system.cpu14.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu14.dcache.ReadReq_miss_rate::cpu14.data 1 # miss rate for ReadReq accesses system.cpu14.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu14.dcache.demand_miss_rate::cpu14.data 1 # miss rate for demand accesses system.cpu14.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu14.dcache.overall_miss_rate::cpu14.data 1 # miss rate for overall accesses system.cpu14.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu14.dcache.ReadReq_avg_miss_latency::cpu14.data 182250 # average ReadReq miss latency system.cpu14.dcache.ReadReq_avg_miss_latency::total 182250 # average ReadReq miss latency system.cpu14.dcache.demand_avg_miss_latency::cpu14.data 182250 # average overall miss latency system.cpu14.dcache.demand_avg_miss_latency::total 182250 # average overall miss latency system.cpu14.dcache.overall_avg_miss_latency::cpu14.data 182250 # average overall miss latency system.cpu14.dcache.overall_avg_miss_latency::total 182250 # average overall miss latency system.cpu14.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu14.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu14.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu14.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu14.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu14.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu14.dcache.ReadReq_mshr_misses::cpu14.data 2 # number of ReadReq MSHR misses system.cpu14.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu14.dcache.demand_mshr_misses::cpu14.data 2 # number of demand (read+write) MSHR misses system.cpu14.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu14.dcache.overall_mshr_misses::cpu14.data 2 # number of overall MSHR misses system.cpu14.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu14.dcache.ReadReq_mshr_miss_latency::cpu14.data 362500 # number of ReadReq MSHR miss cycles system.cpu14.dcache.ReadReq_mshr_miss_latency::total 362500 # number of ReadReq MSHR miss cycles system.cpu14.dcache.demand_mshr_miss_latency::cpu14.data 362500 # number of demand (read+write) MSHR miss cycles system.cpu14.dcache.demand_mshr_miss_latency::total 362500 # number of demand (read+write) MSHR miss cycles system.cpu14.dcache.overall_mshr_miss_latency::cpu14.data 362500 # number of overall MSHR miss cycles system.cpu14.dcache.overall_mshr_miss_latency::total 362500 # number of overall MSHR miss cycles system.cpu14.dcache.ReadReq_mshr_miss_rate::cpu14.data 1 # mshr miss rate for ReadReq accesses system.cpu14.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu14.dcache.demand_mshr_miss_rate::cpu14.data 1 # mshr miss rate for demand accesses system.cpu14.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu14.dcache.overall_mshr_miss_rate::cpu14.data 1 # mshr miss rate for overall accesses system.cpu14.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu14.dcache.ReadReq_avg_mshr_miss_latency::cpu14.data 181250 # average ReadReq mshr miss latency system.cpu14.dcache.ReadReq_avg_mshr_miss_latency::total 181250 # average ReadReq mshr miss latency system.cpu14.dcache.demand_avg_mshr_miss_latency::cpu14.data 181250 # average overall mshr miss latency system.cpu14.dcache.demand_avg_mshr_miss_latency::total 181250 # average overall mshr miss latency system.cpu14.dcache.overall_avg_mshr_miss_latency::cpu14.data 181250 # average overall mshr miss latency system.cpu14.dcache.overall_avg_mshr_miss_latency::total 181250 # average overall mshr miss latency system.cpu14.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu14.icache.tags.replacements 0 # number of replacements system.cpu14.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu14.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu14.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu14.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu14.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu14.icache.tags.occ_blocks::cpu14.inst 1.995860 # Average occupied blocks per requestor system.cpu14.icache.tags.occ_percent::cpu14.inst 0.003898 # Average percentage of cache occupancy system.cpu14.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu14.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu14.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu14.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu14.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu14.icache.tags.data_accesses 622 # Number of data accesses system.cpu14.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu14.icache.ReadReq_hits::cpu14.inst 1 # number of ReadReq hits system.cpu14.icache.ReadReq_hits::switch_cpus14.inst 152 # number of ReadReq hits system.cpu14.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu14.icache.demand_hits::cpu14.inst 1 # number of demand (read+write) hits system.cpu14.icache.demand_hits::switch_cpus14.inst 152 # number of demand (read+write) hits system.cpu14.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu14.icache.overall_hits::cpu14.inst 1 # number of overall hits system.cpu14.icache.overall_hits::switch_cpus14.inst 152 # number of overall hits system.cpu14.icache.overall_hits::total 153 # number of overall hits system.cpu14.icache.ReadReq_misses::cpu14.inst 2 # number of ReadReq misses system.cpu14.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu14.icache.demand_misses::cpu14.inst 2 # number of demand (read+write) misses system.cpu14.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu14.icache.overall_misses::cpu14.inst 2 # number of overall misses system.cpu14.icache.overall_misses::total 2 # number of overall misses system.cpu14.icache.ReadReq_miss_latency::cpu14.inst 164500 # number of ReadReq miss cycles system.cpu14.icache.ReadReq_miss_latency::total 164500 # number of ReadReq miss cycles system.cpu14.icache.demand_miss_latency::cpu14.inst 164500 # number of demand (read+write) miss cycles system.cpu14.icache.demand_miss_latency::total 164500 # number of demand (read+write) miss cycles system.cpu14.icache.overall_miss_latency::cpu14.inst 164500 # number of overall miss cycles system.cpu14.icache.overall_miss_latency::total 164500 # number of overall miss cycles system.cpu14.icache.ReadReq_accesses::cpu14.inst 3 # number of ReadReq accesses(hits+misses) system.cpu14.icache.ReadReq_accesses::switch_cpus14.inst 152 # number of ReadReq accesses(hits+misses) system.cpu14.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu14.icache.demand_accesses::cpu14.inst 3 # number of demand (read+write) accesses system.cpu14.icache.demand_accesses::switch_cpus14.inst 152 # number of demand (read+write) accesses system.cpu14.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu14.icache.overall_accesses::cpu14.inst 3 # number of overall (read+write) accesses system.cpu14.icache.overall_accesses::switch_cpus14.inst 152 # number of overall (read+write) accesses system.cpu14.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu14.icache.ReadReq_miss_rate::cpu14.inst 0.666667 # miss rate for ReadReq accesses system.cpu14.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu14.icache.demand_miss_rate::cpu14.inst 0.666667 # miss rate for demand accesses system.cpu14.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu14.icache.overall_miss_rate::cpu14.inst 0.666667 # miss rate for overall accesses system.cpu14.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu14.icache.ReadReq_avg_miss_latency::cpu14.inst 82250 # average ReadReq miss latency system.cpu14.icache.ReadReq_avg_miss_latency::total 82250 # average ReadReq miss latency system.cpu14.icache.demand_avg_miss_latency::cpu14.inst 82250 # average overall miss latency system.cpu14.icache.demand_avg_miss_latency::total 82250 # average overall miss latency system.cpu14.icache.overall_avg_miss_latency::cpu14.inst 82250 # average overall miss latency system.cpu14.icache.overall_avg_miss_latency::total 82250 # average overall miss latency system.cpu14.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu14.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu14.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu14.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu14.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu14.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu14.icache.ReadReq_mshr_misses::cpu14.inst 2 # number of ReadReq MSHR misses system.cpu14.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu14.icache.demand_mshr_misses::cpu14.inst 2 # number of demand (read+write) MSHR misses system.cpu14.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu14.icache.overall_mshr_misses::cpu14.inst 2 # number of overall MSHR misses system.cpu14.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu14.icache.ReadReq_mshr_miss_latency::cpu14.inst 162500 # number of ReadReq MSHR miss cycles system.cpu14.icache.ReadReq_mshr_miss_latency::total 162500 # number of ReadReq MSHR miss cycles system.cpu14.icache.demand_mshr_miss_latency::cpu14.inst 162500 # number of demand (read+write) MSHR miss cycles system.cpu14.icache.demand_mshr_miss_latency::total 162500 # number of demand (read+write) MSHR miss cycles system.cpu14.icache.overall_mshr_miss_latency::cpu14.inst 162500 # number of overall MSHR miss cycles system.cpu14.icache.overall_mshr_miss_latency::total 162500 # number of overall MSHR miss cycles system.cpu14.icache.ReadReq_mshr_miss_rate::cpu14.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu14.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu14.icache.demand_mshr_miss_rate::cpu14.inst 0.666667 # mshr miss rate for demand accesses system.cpu14.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu14.icache.overall_mshr_miss_rate::cpu14.inst 0.666667 # mshr miss rate for overall accesses system.cpu14.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu14.icache.ReadReq_avg_mshr_miss_latency::cpu14.inst 81250 # average ReadReq mshr miss latency system.cpu14.icache.ReadReq_avg_mshr_miss_latency::total 81250 # average ReadReq mshr miss latency system.cpu14.icache.demand_avg_mshr_miss_latency::cpu14.inst 81250 # average overall mshr miss latency system.cpu14.icache.demand_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu14.icache.overall_avg_mshr_miss_latency::cpu14.inst 81250 # average overall mshr miss latency system.cpu14.icache.overall_avg_mshr_miss_latency::total 81250 # average overall mshr miss latency system.cpu15.branchPred.lookups 5 # Number of BP lookups system.cpu15.branchPred.condPredicted 2 # Number of conditional branches predicted system.cpu15.branchPred.condIncorrect 1 # Number of conditional branches incorrect system.cpu15.branchPred.BTBLookups 1 # Number of BTB lookups system.cpu15.branchPred.BTBHits 0 # Number of BTB hits system.cpu15.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu15.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu15.branchPred.usedRAS 2 # Number of times the RAS was used to get a target. system.cpu15.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu15.branchPred.indirectLookups 1 # Number of indirect predictor lookups. system.cpu15.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu15.branchPred.indirectMisses 1 # Number of indirect misses. system.cpu15.branchPredindirectMispredicted 0 # Number of mispredicted indirect branches. system.cpu15.dtb.fetch_hits 0 # ITB hits system.cpu15.dtb.fetch_misses 0 # ITB misses system.cpu15.dtb.fetch_acv 0 # ITB acv system.cpu15.dtb.fetch_accesses 0 # ITB accesses system.cpu15.dtb.read_hits 2 # DTB read hits system.cpu15.dtb.read_misses 0 # DTB read misses system.cpu15.dtb.read_acv 0 # DTB read access violations system.cpu15.dtb.read_accesses 0 # DTB read accesses system.cpu15.dtb.write_hits 0 # DTB write hits system.cpu15.dtb.write_misses 0 # DTB write misses system.cpu15.dtb.write_acv 0 # DTB write access violations system.cpu15.dtb.write_accesses 0 # DTB write accesses system.cpu15.dtb.data_hits 2 # DTB hits system.cpu15.dtb.data_misses 0 # DTB misses system.cpu15.dtb.data_acv 0 # DTB access violations system.cpu15.dtb.data_accesses 0 # DTB accesses system.cpu15.itb.fetch_hits 0 # ITB hits system.cpu15.itb.fetch_misses 1 # ITB misses system.cpu15.itb.fetch_acv 0 # ITB acv system.cpu15.itb.fetch_accesses 1 # ITB accesses system.cpu15.itb.read_hits 0 # DTB read hits system.cpu15.itb.read_misses 0 # DTB read misses system.cpu15.itb.read_acv 0 # DTB read access violations system.cpu15.itb.read_accesses 0 # DTB read accesses system.cpu15.itb.write_hits 0 # DTB write hits system.cpu15.itb.write_misses 0 # DTB write misses system.cpu15.itb.write_acv 0 # DTB write access violations system.cpu15.itb.write_accesses 0 # DTB write accesses system.cpu15.itb.data_hits 0 # DTB hits system.cpu15.itb.data_misses 0 # DTB misses system.cpu15.itb.data_acv 0 # DTB access violations system.cpu15.itb.data_accesses 0 # DTB accesses system.cpu15.pwrStateResidencyTicks::ON 10000000000 # Cumulative time (in ticks) in various power states system.cpu15.numCycles 501 # number of cpu cycles simulated system.cpu15.numWorkItemsStarted 0 # number of work items this cpu started system.cpu15.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu15.fetch.icacheStallCycles 27 # Number of cycles fetch is stalled on an Icache miss system.cpu15.fetch.Insts 10 # Number of instructions fetch has processed system.cpu15.fetch.Branches 5 # Number of branches that fetch encountered system.cpu15.fetch.predictedBranches 2 # Number of branches that fetch has predicted taken system.cpu15.fetch.Cycles 3 # Number of cycles fetch has run and was not squashing or blocked system.cpu15.fetch.SquashCycles 3 # Number of cycles fetch has spent squashing system.cpu15.fetch.PendingDrainCycles 6 # Number of cycles fetch has spent waiting on pipes to drain system.cpu15.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps system.cpu15.fetch.CacheLines 3 # Number of cache lines fetched system.cpu15.fetch.rateDist::samples 54 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::mean 0.185185 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::stdev 0.912680 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::0 51 94.44% 94.44% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::1 1 1.85% 96.30% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::2 0 0.00% 96.30% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::3 1 1.85% 98.15% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::4 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::5 0 0.00% 98.15% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::6 1 1.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::7 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::8 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::max_value 6 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.rateDist::total 54 # Number of instructions fetched each cycle (Total) system.cpu15.fetch.branchRate 0.009980 # Number of branch fetches per cycle system.cpu15.fetch.rate 0.019960 # Number of inst fetches per cycle system.cpu15.decode.IdleCycles 48 # Number of cycles decode is idle system.cpu15.decode.BlockedCycles 1 # Number of cycles decode is blocked system.cpu15.decode.SquashCycles 2 # Number of cycles decode is squashing system.cpu15.decode.DecodedInsts 11 # Number of instructions handled by decode system.cpu15.rename.SquashCycles 2 # Number of cycles rename is squashing system.cpu15.rename.IdleCycles 47 # Number of cycles rename is idle system.cpu15.rename.BlockCycles 2 # Number of cycles rename is blocking system.cpu15.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst system.cpu15.rename.RunCycles 0 # Number of cycles rename is running system.cpu15.rename.RenamedInsts 11 # Number of instructions processed by rename system.cpu15.rename.RenamedOperands 6 # Number of destination operands rename has renamed system.cpu15.rename.RenameLookups 11 # Number of register rename lookups that rename has made system.cpu15.rename.int_rename_lookups 11 # Number of integer rename lookups system.cpu15.rename.CommittedMaps 1 # Number of HB maps that are committed system.cpu15.rename.UndoneMaps 5 # Number of HB maps that are undone due to squashing system.cpu15.rename.serializingInsts 0 # count of serializing insts renamed system.cpu15.rename.tempSerializingInsts 0 # count of temporary serializing insts renamed system.cpu15.rename.skidInsts 0 # count of insts added to the skid buffer system.cpu15.memDep0.insertedLoads 2 # Number of loads inserted to the mem dependence unit. system.cpu15.memDep0.insertedStores 0 # Number of stores inserted to the mem dependence unit. system.cpu15.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu15.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu15.iq.iqInstsAdded 9 # Number of instructions added to the IQ (excludes non-spec) system.cpu15.iq.iqNonSpecInstsAdded 1 # Number of non-speculative instructions added to the IQ system.cpu15.iq.iqInstsIssued 6 # Number of instructions issued system.cpu15.iq.iqSquashedInstsExamined 9 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu15.iq.iqSquashedOperandsExamined 4 # Number of squashed operands that are examined and possibly removed from graph system.cpu15.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu15.iq.issued_per_cycle::samples 54 # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::mean 0.111111 # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::stdev 0.501570 # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::0 51 94.44% 94.44% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::1 1 1.85% 96.30% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::2 1 1.85% 98.15% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::3 1 1.85% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::4 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::max_value 3 # Number of insts issued each cycle system.cpu15.iq.issued_per_cycle::total 54 # Number of insts issued each cycle system.cpu15.iq.fu_full::No_OpClass 0 # attempts to use FU when none available system.cpu15.iq.fu_full::IntAlu 0 # attempts to use FU when none available system.cpu15.iq.fu_full::IntMult 0 # attempts to use FU when none available system.cpu15.iq.fu_full::IntDiv 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatAdd 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatCmp 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatCvt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatMult 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatMultAcc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatDiv 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatMisc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatSqrt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdAdd 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdAddAcc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdAlu 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdCmp 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdCvt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdMisc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdMult 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdMultAcc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdShift 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdShiftAcc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdSqrt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatAdd 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatAlu 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatCmp 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatCvt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatDiv 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatMisc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatMult 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatMultAcc 0 # attempts to use FU when none available system.cpu15.iq.fu_full::SimdFloatSqrt 0 # attempts to use FU when none available system.cpu15.iq.fu_full::MemRead 0 # attempts to use FU when none available system.cpu15.iq.fu_full::MemWrite 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatMemRead 0 # attempts to use FU when none available system.cpu15.iq.fu_full::FloatMemWrite 0 # attempts to use FU when none available system.cpu15.iq.fu_full::IprAccess 0 # attempts to use FU when none available system.cpu15.iq.fu_full::InstPrefetch 0 # attempts to use FU when none available system.cpu15.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu15.iq.FU_type_0::IntAlu 4 66.67% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::IntMult 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::IntDiv 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatMult 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::FloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdAdd 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdAddAcc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdAlu 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdCmp 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdCvt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdMisc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdMult 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdShift 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdSqrt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatMult 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.67% # Type of FU issued system.cpu15.iq.FU_type_0::MemRead 2 33.33% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::MemWrite 0 0.00% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu15.iq.FU_type_0::total 6 # Type of FU issued system.cpu15.iq.rate 0.011976 # Inst issue rate system.cpu15.iq.fu_busy_cnt 0 # FU busy when requested system.cpu15.iq.fu_busy_rate 0 # FU busy rate (busy events/executed inst) system.cpu15.iq.int_inst_queue_reads 66 # Number of integer instruction queue reads system.cpu15.iq.int_inst_queue_writes 19 # Number of integer instruction queue writes system.cpu15.iq.int_inst_queue_wakeup_accesses 5 # Number of integer instruction queue wakeup accesses system.cpu15.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu15.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu15.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu15.iq.int_alu_accesses 6 # Number of integer alu accesses system.cpu15.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu15.iew.lsq.thread0.forwLoads 0 # Number of loads that had data forwarded from stores system.cpu15.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu15.iew.lsq.thread0.squashedLoads 1 # Number of loads squashed system.cpu15.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu15.iew.lsq.thread0.memOrderViolation 0 # Number of memory ordering violations system.cpu15.iew.lsq.thread0.squashedStores 0 # Number of stores squashed system.cpu15.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu15.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu15.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu15.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu15.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu15.iew.iewSquashCycles 2 # Number of cycles IEW is squashing system.cpu15.iew.iewBlockCycles 2 # Number of cycles IEW is blocking system.cpu15.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu15.iew.iewDispatchedInsts 11 # Number of instructions dispatched to IQ system.cpu15.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu15.iew.iewDispLoadInsts 2 # Number of dispatched load instructions system.cpu15.iew.iewDispStoreInsts 0 # Number of dispatched store instructions system.cpu15.iew.iewDispNonSpecInsts 1 # Number of dispatched non-speculative instructions system.cpu15.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu15.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu15.iew.memOrderViolationEvents 0 # Number of memory order violations system.cpu15.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly system.cpu15.iew.predictedNotTakenIncorrect 1 # Number of branches that were predicted not taken incorrectly system.cpu15.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute system.cpu15.iew.iewExecutedInsts 6 # Number of executed instructions system.cpu15.iew.iewExecLoadInsts 2 # Number of load instructions executed system.cpu15.iew.iewExecSquashedInsts 0 # Number of squashed instructions skipped in execute system.cpu15.iew.exec_swp 0 # number of swp insts executed system.cpu15.iew.exec_nop 1 # number of nop insts executed system.cpu15.iew.exec_refs 2 # number of memory reference insts executed system.cpu15.iew.exec_branches 1 # Number of branches executed system.cpu15.iew.exec_stores 0 # Number of stores executed system.cpu15.iew.exec_rate 0.011976 # Inst execution rate system.cpu15.iew.wb_sent 5 # cumulative count of insts sent to commit system.cpu15.iew.wb_count 5 # cumulative count of insts written-back system.cpu15.iew.wb_producers 1 # num instructions producing a value system.cpu15.iew.wb_consumers 1 # num instructions consuming a value system.cpu15.iew.wb_rate 0.009980 # insts written-back per cycle system.cpu15.iew.wb_fanout 1 # average fanout of values written-back system.cpu15.commit.commitSquashedInsts 10 # The number of squashed insts skipped by commit system.cpu15.commit.branchMispredicts 1 # The number of times a branch was mispredicted system.cpu15.commit.committed_per_cycle::samples 50 # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::mean 0.020000 # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::stdev 0.141421 # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::0 49 98.00% 98.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::1 1 2.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::2 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::3 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::4 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::5 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::6 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::7 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::8 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::max_value 1 # Number of insts commited each cycle system.cpu15.commit.committed_per_cycle::total 50 # Number of insts commited each cycle system.cpu15.commit.committedInsts 1 # Number of instructions committed system.cpu15.commit.committedOps 1 # Number of ops (including micro ops) committed system.cpu15.commit.swp_count 0 # Number of s/w prefetches committed system.cpu15.commit.refs 1 # Number of memory references committed system.cpu15.commit.loads 1 # Number of loads committed system.cpu15.commit.membars 0 # Number of memory barriers committed system.cpu15.commit.branches 0 # Number of branches committed system.cpu15.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu15.commit.int_insts 1 # Number of committed integer instructions. system.cpu15.commit.function_calls 0 # Number of function calls committed. system.cpu15.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::IntAlu 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::IntMult 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::IntDiv 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdAdd 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdAddAcc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdAlu 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdCmp 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdCvt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdMisc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdMult 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdShift 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdShiftAcc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatAdd 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatAlu 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatCmp 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatCvt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatDiv 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatMisc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatMult 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatMultAcc 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::SimdFloatSqrt 0 0.00% 0.00% # Class of committed instruction system.cpu15.commit.op_class_0::MemRead 1 100.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::MemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu15.commit.op_class_0::total 1 # Class of committed instruction system.cpu15.commit.bw_lim_events 0 # number cycles where commit BW limit reached system.cpu15.rob.rob_reads 60 # The number of ROB reads system.cpu15.rob.rob_writes 26 # The number of ROB writes system.cpu15.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu15.idleCycles 447 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu15.quiesceCycles 20041152 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu15.committedInsts 1 # Number of Instructions Simulated system.cpu15.committedOps 1 # Number of Ops (including micro ops) Simulated system.cpu15.cpi 501.000000 # CPI: Cycles Per Instruction system.cpu15.cpi_total 501.000000 # CPI: Total CPI of All Threads system.cpu15.ipc 0.001996 # IPC: Instructions Per Cycle system.cpu15.ipc_total 0.001996 # IPC: Total IPC of All Threads system.cpu15.int_regfile_reads 48 # number of integer regfile reads system.cpu15.int_regfile_writes 4 # number of integer regfile writes system.cpu15.fp_regfile_reads 32 # number of floating regfile reads system.cpu15.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu15.dcache.tags.replacements 0 # number of replacements system.cpu15.dcache.tags.tagsinuse 1.995828 # Cycle average of tags in use system.cpu15.dcache.tags.total_refs 50 # Total number of references to valid blocks. system.cpu15.dcache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu15.dcache.tags.avg_refs 25 # Average number of references to valid blocks. system.cpu15.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu15.dcache.tags.occ_blocks::cpu15.data 1.995828 # Average occupied blocks per requestor system.cpu15.dcache.tags.occ_percent::cpu15.data 0.003898 # Average percentage of cache occupancy system.cpu15.dcache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu15.dcache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu15.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu15.dcache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu15.dcache.tags.tag_accesses 210 # Number of tag accesses system.cpu15.dcache.tags.data_accesses 210 # Number of data accesses system.cpu15.dcache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu15.dcache.ReadReq_hits::switch_cpus15.data 50 # number of ReadReq hits system.cpu15.dcache.ReadReq_hits::total 50 # number of ReadReq hits system.cpu15.dcache.demand_hits::switch_cpus15.data 50 # number of demand (read+write) hits system.cpu15.dcache.demand_hits::total 50 # number of demand (read+write) hits system.cpu15.dcache.overall_hits::switch_cpus15.data 50 # number of overall hits system.cpu15.dcache.overall_hits::total 50 # number of overall hits system.cpu15.dcache.ReadReq_misses::cpu15.data 2 # number of ReadReq misses system.cpu15.dcache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu15.dcache.demand_misses::cpu15.data 2 # number of demand (read+write) misses system.cpu15.dcache.demand_misses::total 2 # number of demand (read+write) misses system.cpu15.dcache.overall_misses::cpu15.data 2 # number of overall misses system.cpu15.dcache.overall_misses::total 2 # number of overall misses system.cpu15.dcache.ReadReq_miss_latency::cpu15.data 310000 # number of ReadReq miss cycles system.cpu15.dcache.ReadReq_miss_latency::total 310000 # number of ReadReq miss cycles system.cpu15.dcache.demand_miss_latency::cpu15.data 310000 # number of demand (read+write) miss cycles system.cpu15.dcache.demand_miss_latency::total 310000 # number of demand (read+write) miss cycles system.cpu15.dcache.overall_miss_latency::cpu15.data 310000 # number of overall miss cycles system.cpu15.dcache.overall_miss_latency::total 310000 # number of overall miss cycles system.cpu15.dcache.ReadReq_accesses::cpu15.data 2 # number of ReadReq accesses(hits+misses) system.cpu15.dcache.ReadReq_accesses::switch_cpus15.data 50 # number of ReadReq accesses(hits+misses) system.cpu15.dcache.ReadReq_accesses::total 52 # number of ReadReq accesses(hits+misses) system.cpu15.dcache.demand_accesses::cpu15.data 2 # number of demand (read+write) accesses system.cpu15.dcache.demand_accesses::switch_cpus15.data 50 # number of demand (read+write) accesses system.cpu15.dcache.demand_accesses::total 52 # number of demand (read+write) accesses system.cpu15.dcache.overall_accesses::cpu15.data 2 # number of overall (read+write) accesses system.cpu15.dcache.overall_accesses::switch_cpus15.data 50 # number of overall (read+write) accesses system.cpu15.dcache.overall_accesses::total 52 # number of overall (read+write) accesses system.cpu15.dcache.ReadReq_miss_rate::cpu15.data 1 # miss rate for ReadReq accesses system.cpu15.dcache.ReadReq_miss_rate::total 0.038462 # miss rate for ReadReq accesses system.cpu15.dcache.demand_miss_rate::cpu15.data 1 # miss rate for demand accesses system.cpu15.dcache.demand_miss_rate::total 0.038462 # miss rate for demand accesses system.cpu15.dcache.overall_miss_rate::cpu15.data 1 # miss rate for overall accesses system.cpu15.dcache.overall_miss_rate::total 0.038462 # miss rate for overall accesses system.cpu15.dcache.ReadReq_avg_miss_latency::cpu15.data 155000 # average ReadReq miss latency system.cpu15.dcache.ReadReq_avg_miss_latency::total 155000 # average ReadReq miss latency system.cpu15.dcache.demand_avg_miss_latency::cpu15.data 155000 # average overall miss latency system.cpu15.dcache.demand_avg_miss_latency::total 155000 # average overall miss latency system.cpu15.dcache.overall_avg_miss_latency::cpu15.data 155000 # average overall miss latency system.cpu15.dcache.overall_avg_miss_latency::total 155000 # average overall miss latency system.cpu15.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu15.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu15.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu15.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu15.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu15.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu15.dcache.ReadReq_mshr_misses::cpu15.data 2 # number of ReadReq MSHR misses system.cpu15.dcache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu15.dcache.demand_mshr_misses::cpu15.data 2 # number of demand (read+write) MSHR misses system.cpu15.dcache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu15.dcache.overall_mshr_misses::cpu15.data 2 # number of overall MSHR misses system.cpu15.dcache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu15.dcache.ReadReq_mshr_miss_latency::cpu15.data 308000 # number of ReadReq MSHR miss cycles system.cpu15.dcache.ReadReq_mshr_miss_latency::total 308000 # number of ReadReq MSHR miss cycles system.cpu15.dcache.demand_mshr_miss_latency::cpu15.data 308000 # number of demand (read+write) MSHR miss cycles system.cpu15.dcache.demand_mshr_miss_latency::total 308000 # number of demand (read+write) MSHR miss cycles system.cpu15.dcache.overall_mshr_miss_latency::cpu15.data 308000 # number of overall MSHR miss cycles system.cpu15.dcache.overall_mshr_miss_latency::total 308000 # number of overall MSHR miss cycles system.cpu15.dcache.ReadReq_mshr_miss_rate::cpu15.data 1 # mshr miss rate for ReadReq accesses system.cpu15.dcache.ReadReq_mshr_miss_rate::total 0.038462 # mshr miss rate for ReadReq accesses system.cpu15.dcache.demand_mshr_miss_rate::cpu15.data 1 # mshr miss rate for demand accesses system.cpu15.dcache.demand_mshr_miss_rate::total 0.038462 # mshr miss rate for demand accesses system.cpu15.dcache.overall_mshr_miss_rate::cpu15.data 1 # mshr miss rate for overall accesses system.cpu15.dcache.overall_mshr_miss_rate::total 0.038462 # mshr miss rate for overall accesses system.cpu15.dcache.ReadReq_avg_mshr_miss_latency::cpu15.data 154000 # average ReadReq mshr miss latency system.cpu15.dcache.ReadReq_avg_mshr_miss_latency::total 154000 # average ReadReq mshr miss latency system.cpu15.dcache.demand_avg_mshr_miss_latency::cpu15.data 154000 # average overall mshr miss latency system.cpu15.dcache.demand_avg_mshr_miss_latency::total 154000 # average overall mshr miss latency system.cpu15.dcache.overall_avg_mshr_miss_latency::cpu15.data 154000 # average overall mshr miss latency system.cpu15.dcache.overall_avg_mshr_miss_latency::total 154000 # average overall mshr miss latency system.cpu15.icache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu15.icache.tags.replacements 0 # number of replacements system.cpu15.icache.tags.tagsinuse 1.995860 # Cycle average of tags in use system.cpu15.icache.tags.total_refs 153 # Total number of references to valid blocks. system.cpu15.icache.tags.sampled_refs 2 # Sample count of references to valid blocks. system.cpu15.icache.tags.avg_refs 76.500000 # Average number of references to valid blocks. system.cpu15.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu15.icache.tags.occ_blocks::cpu15.inst 1.995860 # Average occupied blocks per requestor system.cpu15.icache.tags.occ_percent::cpu15.inst 0.003898 # Average percentage of cache occupancy system.cpu15.icache.tags.occ_percent::total 0.003898 # Average percentage of cache occupancy system.cpu15.icache.tags.occ_task_id_blocks::1024 2 # Occupied blocks per task id system.cpu15.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu15.icache.tags.occ_task_id_percent::1024 0.003906 # Percentage of cache occupancy per task id system.cpu15.icache.tags.tag_accesses 622 # Number of tag accesses system.cpu15.icache.tags.data_accesses 622 # Number of data accesses system.cpu15.icache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu15.icache.ReadReq_hits::cpu15.inst 1 # number of ReadReq hits system.cpu15.icache.ReadReq_hits::switch_cpus15.inst 152 # number of ReadReq hits system.cpu15.icache.ReadReq_hits::total 153 # number of ReadReq hits system.cpu15.icache.demand_hits::cpu15.inst 1 # number of demand (read+write) hits system.cpu15.icache.demand_hits::switch_cpus15.inst 152 # number of demand (read+write) hits system.cpu15.icache.demand_hits::total 153 # number of demand (read+write) hits system.cpu15.icache.overall_hits::cpu15.inst 1 # number of overall hits system.cpu15.icache.overall_hits::switch_cpus15.inst 152 # number of overall hits system.cpu15.icache.overall_hits::total 153 # number of overall hits system.cpu15.icache.ReadReq_misses::cpu15.inst 2 # number of ReadReq misses system.cpu15.icache.ReadReq_misses::total 2 # number of ReadReq misses system.cpu15.icache.demand_misses::cpu15.inst 2 # number of demand (read+write) misses system.cpu15.icache.demand_misses::total 2 # number of demand (read+write) misses system.cpu15.icache.overall_misses::cpu15.inst 2 # number of overall misses system.cpu15.icache.overall_misses::total 2 # number of overall misses system.cpu15.icache.ReadReq_miss_latency::cpu15.inst 164000 # number of ReadReq miss cycles system.cpu15.icache.ReadReq_miss_latency::total 164000 # number of ReadReq miss cycles system.cpu15.icache.demand_miss_latency::cpu15.inst 164000 # number of demand (read+write) miss cycles system.cpu15.icache.demand_miss_latency::total 164000 # number of demand (read+write) miss cycles system.cpu15.icache.overall_miss_latency::cpu15.inst 164000 # number of overall miss cycles system.cpu15.icache.overall_miss_latency::total 164000 # number of overall miss cycles system.cpu15.icache.ReadReq_accesses::cpu15.inst 3 # number of ReadReq accesses(hits+misses) system.cpu15.icache.ReadReq_accesses::switch_cpus15.inst 152 # number of ReadReq accesses(hits+misses) system.cpu15.icache.ReadReq_accesses::total 155 # number of ReadReq accesses(hits+misses) system.cpu15.icache.demand_accesses::cpu15.inst 3 # number of demand (read+write) accesses system.cpu15.icache.demand_accesses::switch_cpus15.inst 152 # number of demand (read+write) accesses system.cpu15.icache.demand_accesses::total 155 # number of demand (read+write) accesses system.cpu15.icache.overall_accesses::cpu15.inst 3 # number of overall (read+write) accesses system.cpu15.icache.overall_accesses::switch_cpus15.inst 152 # number of overall (read+write) accesses system.cpu15.icache.overall_accesses::total 155 # number of overall (read+write) accesses system.cpu15.icache.ReadReq_miss_rate::cpu15.inst 0.666667 # miss rate for ReadReq accesses system.cpu15.icache.ReadReq_miss_rate::total 0.012903 # miss rate for ReadReq accesses system.cpu15.icache.demand_miss_rate::cpu15.inst 0.666667 # miss rate for demand accesses system.cpu15.icache.demand_miss_rate::total 0.012903 # miss rate for demand accesses system.cpu15.icache.overall_miss_rate::cpu15.inst 0.666667 # miss rate for overall accesses system.cpu15.icache.overall_miss_rate::total 0.012903 # miss rate for overall accesses system.cpu15.icache.ReadReq_avg_miss_latency::cpu15.inst 82000 # average ReadReq miss latency system.cpu15.icache.ReadReq_avg_miss_latency::total 82000 # average ReadReq miss latency system.cpu15.icache.demand_avg_miss_latency::cpu15.inst 82000 # average overall miss latency system.cpu15.icache.demand_avg_miss_latency::total 82000 # average overall miss latency system.cpu15.icache.overall_avg_miss_latency::cpu15.inst 82000 # average overall miss latency system.cpu15.icache.overall_avg_miss_latency::total 82000 # average overall miss latency system.cpu15.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu15.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu15.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu15.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu15.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu15.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu15.icache.ReadReq_mshr_misses::cpu15.inst 2 # number of ReadReq MSHR misses system.cpu15.icache.ReadReq_mshr_misses::total 2 # number of ReadReq MSHR misses system.cpu15.icache.demand_mshr_misses::cpu15.inst 2 # number of demand (read+write) MSHR misses system.cpu15.icache.demand_mshr_misses::total 2 # number of demand (read+write) MSHR misses system.cpu15.icache.overall_mshr_misses::cpu15.inst 2 # number of overall MSHR misses system.cpu15.icache.overall_mshr_misses::total 2 # number of overall MSHR misses system.cpu15.icache.ReadReq_mshr_miss_latency::cpu15.inst 162000 # number of ReadReq MSHR miss cycles system.cpu15.icache.ReadReq_mshr_miss_latency::total 162000 # number of ReadReq MSHR miss cycles system.cpu15.icache.demand_mshr_miss_latency::cpu15.inst 162000 # number of demand (read+write) MSHR miss cycles system.cpu15.icache.demand_mshr_miss_latency::total 162000 # number of demand (read+write) MSHR miss cycles system.cpu15.icache.overall_mshr_miss_latency::cpu15.inst 162000 # number of overall MSHR miss cycles system.cpu15.icache.overall_mshr_miss_latency::total 162000 # number of overall MSHR miss cycles system.cpu15.icache.ReadReq_mshr_miss_rate::cpu15.inst 0.666667 # mshr miss rate for ReadReq accesses system.cpu15.icache.ReadReq_mshr_miss_rate::total 0.012903 # mshr miss rate for ReadReq accesses system.cpu15.icache.demand_mshr_miss_rate::cpu15.inst 0.666667 # mshr miss rate for demand accesses system.cpu15.icache.demand_mshr_miss_rate::total 0.012903 # mshr miss rate for demand accesses system.cpu15.icache.overall_mshr_miss_rate::cpu15.inst 0.666667 # mshr miss rate for overall accesses system.cpu15.icache.overall_mshr_miss_rate::total 0.012903 # mshr miss rate for overall accesses system.cpu15.icache.ReadReq_avg_mshr_miss_latency::cpu15.inst 81000 # average ReadReq mshr miss latency system.cpu15.icache.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency system.cpu15.icache.demand_avg_mshr_miss_latency::cpu15.inst 81000 # average overall mshr miss latency system.cpu15.icache.demand_avg_mshr_miss_latency::total 81000 # average overall mshr miss latency system.cpu15.icache.overall_avg_mshr_miss_latency::cpu15.inst 81000 # average overall mshr miss latency system.cpu15.icache.overall_avg_mshr_miss_latency::total 81000 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. system.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.disk0.dma_write_txs 0 # Number of DMA write transactions. system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. system.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 0 # Number of DMA write transactions. system.iobus.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 943 # Transaction distribution system.iobus.trans_dist::ReadResp 943 # Transaction distribution system.iobus.trans_dist::WriteReq 987 # Transaction distribution system.iobus.trans_dist::WriteResp 987 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 48 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 3746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 3860 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 3860 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 192 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 1873 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 2098 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2098 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2.tags.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.l2.tags.replacements 0 # number of replacements system.l2.tags.tagsinuse 74275.501728 # Cycle average of tags in use system.l2.tags.total_refs 365364 # Total number of references to valid blocks. system.l2.tags.sampled_refs 147980 # Sample count of references to valid blocks. system.l2.tags.avg_refs 2.469009 # Average number of references to valid blocks. system.l2.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2.tags.occ_blocks::cpu00.inst 1.999975 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu00.data 0.999983 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu01.data 0.997912 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu02.data 0.997913 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu03.data 0.997913 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu04.data 0.997919 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu05.data 0.997918 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu06.data 0.997918 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu07.data 0.997917 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu08.data 0.997917 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu09.data 0.997916 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu10.data 0.997916 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu11.data 0.997915 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu12.data 0.997915 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu13.data 0.997914 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu14.data 0.997914 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu15.inst 1.995862 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu15.data 1.995831 # Average occupied blocks per requestor system.l2.tags.occ_blocks::switch_cpus00.inst 714.974377 # Average occupied blocks per requestor system.l2.tags.occ_blocks::switch_cpus00.data 73539.564887 # Average occupied blocks per requestor system.l2.tags.occ_percent::cpu00.inst 0.000008 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu00.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu01.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu02.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu03.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu04.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu05.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu06.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu07.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu08.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu09.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu10.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu11.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu12.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu13.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu14.data 0.000004 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu15.inst 0.000008 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu15.data 0.000008 # Average percentage of cache occupancy system.l2.tags.occ_percent::switch_cpus00.inst 0.002727 # Average percentage of cache occupancy system.l2.tags.occ_percent::switch_cpus00.data 0.280531 # Average percentage of cache occupancy system.l2.tags.occ_percent::total 0.283339 # Average percentage of cache occupancy system.l2.tags.occ_task_id_blocks::1024 147980 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::3 147980 # Occupied blocks per task id system.l2.tags.occ_task_id_percent::1024 0.564499 # Percentage of cache occupancy per task id system.l2.tags.tag_accesses 2201488 # Number of tag accesses system.l2.tags.data_accesses 2201488 # Number of data accesses system.l2.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.l2.WritebackDirty_hits::writebacks 252639 # number of WritebackDirty hits system.l2.WritebackDirty_hits::total 252639 # number of WritebackDirty hits system.l2.WritebackClean_hits::writebacks 578 # number of WritebackClean hits system.l2.WritebackClean_hits::total 578 # number of WritebackClean hits system.l2.ReadExReq_hits::switch_cpus00.data 30679 # number of ReadExReq hits system.l2.ReadExReq_hits::total 30679 # number of ReadExReq hits system.l2.ReadCleanReq_hits::cpu01.inst 2 # number of ReadCleanReq hits system.l2.ReadCleanReq_hits::cpu02.inst 2 # number of ReadCleanReq hits system.l2.ReadCleanReq_hits::cpu03.inst 2 # number of ReadCleanReq hits system.l2.ReadCleanReq_hits::switch_cpus00.inst 172 # number of ReadCleanReq hits system.l2.ReadCleanReq_hits::total 178 # number of ReadCleanReq hits system.l2.ReadSharedReq_hits::cpu01.data 1 # number of ReadSharedReq hits system.l2.ReadSharedReq_hits::cpu02.data 1 # number of ReadSharedReq hits system.l2.ReadSharedReq_hits::cpu03.data 1 # number of ReadSharedReq hits system.l2.ReadSharedReq_hits::switch_cpus00.data 78352 # number of ReadSharedReq hits system.l2.ReadSharedReq_hits::total 78355 # number of ReadSharedReq hits system.l2.demand_hits::cpu01.inst 2 # number of demand (read+write) hits system.l2.demand_hits::cpu01.data 1 # number of demand (read+write) hits system.l2.demand_hits::cpu02.inst 2 # number of demand (read+write) hits system.l2.demand_hits::cpu02.data 1 # number of demand (read+write) hits system.l2.demand_hits::cpu03.inst 2 # number of demand (read+write) hits system.l2.demand_hits::cpu03.data 1 # number of demand (read+write) hits system.l2.demand_hits::switch_cpus00.inst 172 # number of demand (read+write) hits system.l2.demand_hits::switch_cpus00.data 109031 # number of demand (read+write) hits system.l2.demand_hits::total 109212 # number of demand (read+write) hits system.l2.overall_hits::cpu01.inst 2 # number of overall hits system.l2.overall_hits::cpu01.data 1 # number of overall hits system.l2.overall_hits::cpu02.inst 2 # number of overall hits system.l2.overall_hits::cpu02.data 1 # number of overall hits system.l2.overall_hits::cpu03.inst 2 # number of overall hits system.l2.overall_hits::cpu03.data 1 # number of overall hits system.l2.overall_hits::switch_cpus00.inst 172 # number of overall hits system.l2.overall_hits::switch_cpus00.data 109031 # number of overall hits system.l2.overall_hits::total 109212 # number of overall hits system.l2.ReadExReq_misses::switch_cpus00.data 61058 # number of ReadExReq misses system.l2.ReadExReq_misses::total 61058 # number of ReadExReq misses system.l2.ReadCleanReq_misses::cpu00.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu04.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu05.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu06.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu07.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu08.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu09.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu10.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu11.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu12.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu13.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu14.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::cpu15.inst 2 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::switch_cpus00.inst 905 # number of ReadCleanReq misses system.l2.ReadCleanReq_misses::total 931 # number of ReadCleanReq misses system.l2.ReadSharedReq_misses::cpu00.data 1 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu01.data 1 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu02.data 1 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu03.data 1 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu04.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu05.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu06.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu07.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu08.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu09.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu10.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu11.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu12.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu13.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu14.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::cpu15.data 2 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::switch_cpus00.data 85996 # number of ReadSharedReq misses system.l2.ReadSharedReq_misses::total 86024 # number of ReadSharedReq misses system.l2.demand_misses::cpu00.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu00.data 1 # number of demand (read+write) misses system.l2.demand_misses::cpu01.data 1 # number of demand (read+write) misses system.l2.demand_misses::cpu02.data 1 # number of demand (read+write) misses system.l2.demand_misses::cpu03.data 1 # number of demand (read+write) misses system.l2.demand_misses::cpu04.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu04.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu05.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu05.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu06.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu06.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu07.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu07.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu08.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu08.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu09.inst 2 # number of demand (read+write) misses system.l2.demand_misses::cpu09.data 2 # number of demand (read+write) misses system.l2.demand_misses::cpu10.inst 2 # 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number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu06.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu07.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu08.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu09.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu10.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu11.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu12.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu13.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu14.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::cpu15.inst 2 # number of ReadCleanReq accesses(hits+misses) system.l2.ReadCleanReq_accesses::switch_cpus00.inst 1077 # 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number of ReadSharedReq MSHR misses system.l2.ReadSharedReq_mshr_misses::cpu15.data 2 # number of ReadSharedReq MSHR misses system.l2.ReadSharedReq_mshr_misses::total 17 # number of ReadSharedReq MSHR misses system.l2.demand_mshr_misses::cpu00.inst 2 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu00.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu01.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu02.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu03.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu04.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu05.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu06.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu07.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu08.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu09.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu10.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu11.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu12.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu13.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu14.data 1 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu15.inst 2 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::cpu15.data 2 # number of demand (read+write) MSHR misses system.l2.demand_mshr_misses::total 21 # number of demand (read+write) MSHR misses system.l2.overall_mshr_misses::cpu00.inst 2 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu00.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu01.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu02.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu03.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu04.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu05.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu06.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu07.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu08.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu09.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu10.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu11.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu12.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu13.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu14.data 1 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu15.inst 2 # number of overall MSHR misses system.l2.overall_mshr_misses::cpu15.data 2 # number of overall MSHR misses system.l2.overall_mshr_misses::total 21 # number of overall MSHR misses system.l2.ReadCleanReq_mshr_miss_latency::cpu00.inst 155000 # number of ReadCleanReq MSHR miss cycles system.l2.ReadCleanReq_mshr_miss_latency::cpu15.inst 139000 # number of ReadCleanReq MSHR miss cycles system.l2.ReadCleanReq_mshr_miss_latency::total 294000 # number of ReadCleanReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu00.data 74000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu01.data 142000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu02.data 133000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu03.data 137500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu04.data 85000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu05.data 89500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu06.data 94000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu07.data 98500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu08.data 103000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu09.data 107500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu10.data 112000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu11.data 116500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu12.data 121000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu13.data 125500 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu14.data 130000 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::cpu15.data 221999 # number of ReadSharedReq MSHR miss cycles system.l2.ReadSharedReq_mshr_miss_latency::total 1890999 # number of ReadSharedReq MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu00.inst 155000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu00.data 74000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu01.data 142000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu02.data 133000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu03.data 137500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu04.data 85000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu05.data 89500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu06.data 94000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu07.data 98500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu08.data 103000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu09.data 107500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu10.data 112000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu11.data 116500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu12.data 121000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu13.data 125500 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu14.data 130000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu15.inst 139000 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::cpu15.data 221999 # number of demand (read+write) MSHR miss cycles system.l2.demand_mshr_miss_latency::total 2184999 # number of demand (read+write) MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu00.inst 155000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu00.data 74000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu01.data 142000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu02.data 133000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu03.data 137500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu04.data 85000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu05.data 89500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu06.data 94000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu07.data 98500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu08.data 103000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu09.data 107500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu10.data 112000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu11.data 116500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu12.data 121000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu13.data 125500 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu14.data 130000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu15.inst 139000 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::cpu15.data 221999 # number of overall MSHR miss cycles system.l2.overall_mshr_miss_latency::total 2184999 # number of overall MSHR miss cycles system.l2.ReadCleanReq_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for ReadCleanReq accesses system.l2.ReadCleanReq_mshr_miss_rate::cpu15.inst 1 # mshr miss rate for ReadCleanReq accesses system.l2.ReadCleanReq_mshr_miss_rate::total 0.003607 # mshr miss rate for ReadCleanReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu00.data 1 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu01.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu02.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu03.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu04.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu05.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu06.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu07.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu08.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu09.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu10.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu11.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu12.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu13.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu14.data 0.500000 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::cpu15.data 1 # mshr miss rate for ReadSharedReq accesses system.l2.ReadSharedReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadSharedReq accesses system.l2.demand_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu00.data 1 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu01.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu02.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu03.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu04.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu05.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu06.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu07.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu08.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu09.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu10.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu11.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu12.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu13.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu14.data 0.500000 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu15.inst 1 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::cpu15.data 1 # mshr miss rate for demand accesses system.l2.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses system.l2.overall_mshr_miss_rate::cpu00.inst 1 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu00.data 1 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu01.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu02.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu03.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu04.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu05.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu06.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu07.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu08.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu09.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu10.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu11.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu12.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu13.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu14.data 0.500000 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu15.inst 1 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::cpu15.data 1 # mshr miss rate for overall accesses system.l2.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses system.l2.ReadCleanReq_avg_mshr_miss_latency::cpu00.inst 77500 # average ReadCleanReq mshr miss latency system.l2.ReadCleanReq_avg_mshr_miss_latency::cpu15.inst 69500 # average ReadCleanReq mshr miss latency system.l2.ReadCleanReq_avg_mshr_miss_latency::total 73500 # average ReadCleanReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu00.data 74000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu01.data 142000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu02.data 133000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu03.data 137500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu04.data 85000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu05.data 89500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu06.data 94000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu07.data 98500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu08.data 103000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu09.data 107500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu10.data 112000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu11.data 116500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu12.data 121000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu13.data 125500 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu14.data 130000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::cpu15.data 110999.500000 # average ReadSharedReq mshr miss latency system.l2.ReadSharedReq_avg_mshr_miss_latency::total 111235.235294 # average ReadSharedReq mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu00.inst 77500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu00.data 74000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu01.data 142000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu02.data 133000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu03.data 137500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu04.data 85000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu05.data 89500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu06.data 94000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu07.data 98500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu08.data 103000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu09.data 107500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu10.data 112000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu11.data 116500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu12.data 121000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu13.data 125500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu14.data 130000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu15.inst 69500 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::cpu15.data 110999.500000 # average overall mshr miss latency system.l2.demand_avg_mshr_miss_latency::total 104047.571429 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu00.inst 77500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu00.data 74000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu01.data 142000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu02.data 133000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu03.data 137500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu04.data 85000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu05.data 89500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu06.data 94000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu07.data 98500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu08.data 103000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu09.data 107500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu10.data 112000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu11.data 116500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu12.data 121000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu13.data 125500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu14.data 130000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu15.inst 69500 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::cpu15.data 110999.500000 # average overall mshr miss latency system.l2.overall_avg_mshr_miss_latency::total 104047.571429 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 147980 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 943 # Transaction distribution system.membus.trans_dist::ReadResp 87865 # Transaction distribution system.membus.trans_dist::WriteReq 987 # Transaction distribution system.membus.trans_dist::WriteResp 987 # Transaction distribution system.membus.trans_dist::ReadExReq 61058 # Transaction distribution system.membus.trans_dist::ReadExResp 61058 # Transaction distribution system.membus.trans_dist::ReadSharedReq 86922 # Transaction distribution system.membus.pkt_count_system.l2.mem_side::system.bridge.slave 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 295960 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2.mem_side::total 299820 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 299820 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2.mem_side::system.bridge.slave 2098 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 9470720 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2.mem_side::total 9472818 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 9472818 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 149910 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 149910 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 149910 # Request fanout histogram system.membus.reqLayer1.occupancy 22001 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 108000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.switch_cpus00.dtb.fetch_hits 0 # ITB hits system.switch_cpus00.dtb.fetch_misses 0 # ITB misses system.switch_cpus00.dtb.fetch_acv 0 # ITB acv system.switch_cpus00.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus00.dtb.read_hits 2317729 # DTB read hits system.switch_cpus00.dtb.read_misses 0 # DTB read misses system.switch_cpus00.dtb.read_acv 0 # DTB read access violations system.switch_cpus00.dtb.read_accesses 0 # DTB read accesses system.switch_cpus00.dtb.write_hits 967205 # DTB write hits system.switch_cpus00.dtb.write_misses 0 # DTB write misses system.switch_cpus00.dtb.write_acv 0 # DTB write access violations system.switch_cpus00.dtb.write_accesses 0 # DTB write accesses system.switch_cpus00.dtb.data_hits 3284934 # DTB hits system.switch_cpus00.dtb.data_misses 0 # DTB misses system.switch_cpus00.dtb.data_acv 0 # DTB access violations system.switch_cpus00.dtb.data_accesses 0 # DTB accesses system.switch_cpus00.itb.fetch_hits 40909 # ITB hits system.switch_cpus00.itb.fetch_misses 0 # ITB misses system.switch_cpus00.itb.fetch_acv 0 # ITB acv system.switch_cpus00.itb.fetch_accesses 40909 # ITB accesses system.switch_cpus00.itb.read_hits 0 # DTB read hits system.switch_cpus00.itb.read_misses 0 # DTB read misses system.switch_cpus00.itb.read_acv 0 # DTB read access violations system.switch_cpus00.itb.read_accesses 0 # DTB read accesses system.switch_cpus00.itb.write_hits 0 # DTB write hits system.switch_cpus00.itb.write_misses 0 # DTB write misses system.switch_cpus00.itb.write_acv 0 # DTB write access violations system.switch_cpus00.itb.write_accesses 0 # DTB write accesses system.switch_cpus00.itb.data_hits 0 # DTB hits system.switch_cpus00.itb.data_misses 0 # DTB misses system.switch_cpus00.itb.data_acv 0 # DTB access violations system.switch_cpus00.itb.data_accesses 0 # DTB accesses system.switch_cpus00.numPwrStateTransitions 1836 # Number of power state transitions system.switch_cpus00.pwrStateClkGateDist::samples 918 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::mean 3176470.588235 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::stdev 65976874.160727 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::1000-5e+10 918 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::min_value 91000 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateClkGateDist::total 918 # Distribution of time spent in the clock gated state system.switch_cpus00.pwrStateResidencyTicks::ON 7084000000 # Cumulative time (in ticks) in various power states system.switch_cpus00.pwrStateResidencyTicks::CLK_GATED 2916000000 # Cumulative time (in ticks) in various power states system.switch_cpus00.numCycles 19953641 # number of cpu cycles simulated system.switch_cpus00.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus00.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus00.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus00.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus00.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus00.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus00.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus00.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus00.kern.mode_good::kernel 0 system.switch_cpus00.kern.mode_good::user 0 system.switch_cpus00.kern.mode_good::idle 0 system.switch_cpus00.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus00.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus00.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus00.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus00.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus00.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus00.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus00.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus00.committedInsts 14121641 # Number of instructions committed system.switch_cpus00.committedOps 14121641 # Number of ops (including micro ops) committed system.switch_cpus00.num_int_alu_accesses 14078018 # Number of integer alu accesses system.switch_cpus00.num_fp_alu_accesses 128576 # Number of float alu accesses system.switch_cpus00.num_func_calls 229863 # number of times a function call or return occured system.switch_cpus00.num_conditional_control_insts 2082607 # number of instructions that are conditional controls system.switch_cpus00.num_int_insts 14078018 # number of integer instructions system.switch_cpus00.num_fp_insts 128576 # number of float instructions system.switch_cpus00.num_int_register_reads 20111570 # number of times the integer registers were read system.switch_cpus00.num_int_register_writes 10819547 # number of times the integer registers were written system.switch_cpus00.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus00.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus00.num_mem_refs 3284942 # number of memory refs system.switch_cpus00.num_load_insts 2317729 # Number of load instructions system.switch_cpus00.num_store_insts 967213 # Number of store instructions system.switch_cpus00.num_idle_cycles 5865649.129291 # Number of idle cycles system.switch_cpus00.num_busy_cycles 14087991.870709 # Number of busy cycles system.switch_cpus00.not_idle_fraction 0.706036 # Percentage of non-idle cycles system.switch_cpus00.idle_fraction 0.293964 # Percentage of idle cycles system.switch_cpus00.Branches 2333964 # Number of branches fetched system.switch_cpus00.op_class::No_OpClass 6995 0.05% 0.05% # Class of executed instruction system.switch_cpus00.op_class::IntAlu 10646045 75.39% 75.44% # Class of executed instruction system.switch_cpus00.op_class::IntMult 26146 0.19% 75.62% # Class of executed instruction system.switch_cpus00.op_class::IntDiv 0 0.00% 75.62% # Class of executed instruction system.switch_cpus00.op_class::FloatAdd 128576 0.91% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatCmp 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatCvt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatMult 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatMultAcc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatDiv 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatMisc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::FloatSqrt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdAdd 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdAddAcc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdAlu 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdCmp 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdCvt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdMisc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdMult 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdMultAcc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdShift 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdShiftAcc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdSqrt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatAdd 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatAlu 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatCmp 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatCvt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatDiv 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatMisc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatMult 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatMultAcc 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::SimdFloatSqrt 0 0.00% 76.53% # Class of executed instruction system.switch_cpus00.op_class::MemRead 2328651 16.49% 93.02% # Class of executed instruction system.switch_cpus00.op_class::MemWrite 967235 6.85% 99.87% # Class of executed instruction system.switch_cpus00.op_class::FloatMemRead 0 0.00% 99.87% # Class of executed instruction system.switch_cpus00.op_class::FloatMemWrite 0 0.00% 99.87% # Class of executed instruction system.switch_cpus00.op_class::IprAccess 17993 0.13% 100.00% # Class of executed instruction system.switch_cpus00.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus00.op_class::total 14121641 # Class of executed instruction system.switch_cpus01.dtb.fetch_hits 0 # ITB hits system.switch_cpus01.dtb.fetch_misses 0 # ITB misses system.switch_cpus01.dtb.fetch_acv 0 # ITB acv system.switch_cpus01.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus01.dtb.read_hits 50 # DTB read hits system.switch_cpus01.dtb.read_misses 0 # DTB read misses system.switch_cpus01.dtb.read_acv 0 # DTB read access violations system.switch_cpus01.dtb.read_accesses 0 # DTB read accesses system.switch_cpus01.dtb.write_hits 0 # DTB write hits system.switch_cpus01.dtb.write_misses 0 # DTB write misses system.switch_cpus01.dtb.write_acv 0 # DTB write access violations system.switch_cpus01.dtb.write_accesses 0 # DTB write accesses system.switch_cpus01.dtb.data_hits 50 # DTB hits system.switch_cpus01.dtb.data_misses 0 # DTB misses system.switch_cpus01.dtb.data_acv 0 # DTB access violations system.switch_cpus01.dtb.data_accesses 0 # DTB accesses system.switch_cpus01.itb.fetch_hits 0 # ITB hits system.switch_cpus01.itb.fetch_misses 0 # ITB misses system.switch_cpus01.itb.fetch_acv 0 # ITB acv system.switch_cpus01.itb.fetch_accesses 0 # ITB accesses system.switch_cpus01.itb.read_hits 0 # DTB read hits system.switch_cpus01.itb.read_misses 0 # DTB read misses system.switch_cpus01.itb.read_acv 0 # DTB read access violations system.switch_cpus01.itb.read_accesses 0 # DTB read accesses system.switch_cpus01.itb.write_hits 0 # DTB write hits system.switch_cpus01.itb.write_misses 0 # DTB write misses system.switch_cpus01.itb.write_acv 0 # DTB write access violations system.switch_cpus01.itb.write_accesses 0 # DTB write accesses system.switch_cpus01.itb.data_hits 0 # DTB hits system.switch_cpus01.itb.data_misses 0 # DTB misses system.switch_cpus01.itb.data_acv 0 # DTB access violations system.switch_cpus01.itb.data_accesses 0 # DTB accesses system.switch_cpus01.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus01.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus01.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus01.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus01.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus01.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus01.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus01.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus01.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus01.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus01.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus01.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus01.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus01.kern.mode_good::kernel 0 system.switch_cpus01.kern.mode_good::user 0 system.switch_cpus01.kern.mode_good::idle 0 system.switch_cpus01.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus01.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus01.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus01.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus01.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus01.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus01.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus01.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus01.committedInsts 152 # Number of instructions committed system.switch_cpus01.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus01.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus01.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus01.num_func_calls 0 # number of times a function call or return occured system.switch_cpus01.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus01.num_int_insts 101 # number of integer instructions system.switch_cpus01.num_fp_insts 0 # number of float instructions system.switch_cpus01.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus01.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus01.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus01.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus01.num_mem_refs 50 # number of memory refs system.switch_cpus01.num_load_insts 50 # Number of load instructions system.switch_cpus01.num_store_insts 0 # Number of store instructions system.switch_cpus01.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus01.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus01.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus01.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus01.Branches 51 # Number of branches fetched system.switch_cpus01.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus01.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus01.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus01.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus01.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus01.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus01.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus01.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus01.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus01.op_class::total 152 # Class of executed instruction system.switch_cpus02.dtb.fetch_hits 0 # ITB hits system.switch_cpus02.dtb.fetch_misses 0 # ITB misses system.switch_cpus02.dtb.fetch_acv 0 # ITB acv system.switch_cpus02.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus02.dtb.read_hits 50 # DTB read hits system.switch_cpus02.dtb.read_misses 0 # DTB read misses system.switch_cpus02.dtb.read_acv 0 # DTB read access violations system.switch_cpus02.dtb.read_accesses 0 # DTB read accesses system.switch_cpus02.dtb.write_hits 0 # DTB write hits system.switch_cpus02.dtb.write_misses 0 # DTB write misses system.switch_cpus02.dtb.write_acv 0 # DTB write access violations system.switch_cpus02.dtb.write_accesses 0 # DTB write accesses system.switch_cpus02.dtb.data_hits 50 # DTB hits system.switch_cpus02.dtb.data_misses 0 # DTB misses system.switch_cpus02.dtb.data_acv 0 # DTB access violations system.switch_cpus02.dtb.data_accesses 0 # DTB accesses system.switch_cpus02.itb.fetch_hits 0 # ITB hits system.switch_cpus02.itb.fetch_misses 0 # ITB misses system.switch_cpus02.itb.fetch_acv 0 # ITB acv system.switch_cpus02.itb.fetch_accesses 0 # ITB accesses system.switch_cpus02.itb.read_hits 0 # DTB read hits system.switch_cpus02.itb.read_misses 0 # DTB read misses system.switch_cpus02.itb.read_acv 0 # DTB read access violations system.switch_cpus02.itb.read_accesses 0 # DTB read accesses system.switch_cpus02.itb.write_hits 0 # DTB write hits system.switch_cpus02.itb.write_misses 0 # DTB write misses system.switch_cpus02.itb.write_acv 0 # DTB write access violations system.switch_cpus02.itb.write_accesses 0 # DTB write accesses system.switch_cpus02.itb.data_hits 0 # DTB hits system.switch_cpus02.itb.data_misses 0 # DTB misses system.switch_cpus02.itb.data_acv 0 # DTB access violations system.switch_cpus02.itb.data_accesses 0 # DTB accesses system.switch_cpus02.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus02.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus02.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus02.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus02.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus02.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus02.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus02.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus02.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus02.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus02.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus02.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus02.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus02.kern.mode_good::kernel 0 system.switch_cpus02.kern.mode_good::user 0 system.switch_cpus02.kern.mode_good::idle 0 system.switch_cpus02.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus02.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus02.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus02.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus02.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus02.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus02.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus02.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus02.committedInsts 152 # Number of instructions committed system.switch_cpus02.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus02.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus02.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus02.num_func_calls 0 # number of times a function call or return occured system.switch_cpus02.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus02.num_int_insts 101 # number of integer instructions system.switch_cpus02.num_fp_insts 0 # number of float instructions system.switch_cpus02.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus02.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus02.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus02.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus02.num_mem_refs 50 # number of memory refs system.switch_cpus02.num_load_insts 50 # Number of load instructions system.switch_cpus02.num_store_insts 0 # Number of store instructions system.switch_cpus02.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus02.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus02.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus02.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus02.Branches 51 # Number of branches fetched system.switch_cpus02.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus02.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus02.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus02.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus02.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus02.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus02.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus02.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus02.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus02.op_class::total 152 # Class of executed instruction system.switch_cpus03.dtb.fetch_hits 0 # ITB hits system.switch_cpus03.dtb.fetch_misses 0 # ITB misses system.switch_cpus03.dtb.fetch_acv 0 # ITB acv system.switch_cpus03.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus03.dtb.read_hits 50 # DTB read hits system.switch_cpus03.dtb.read_misses 0 # DTB read misses system.switch_cpus03.dtb.read_acv 0 # DTB read access violations system.switch_cpus03.dtb.read_accesses 0 # DTB read accesses system.switch_cpus03.dtb.write_hits 0 # DTB write hits system.switch_cpus03.dtb.write_misses 0 # DTB write misses system.switch_cpus03.dtb.write_acv 0 # DTB write access violations system.switch_cpus03.dtb.write_accesses 0 # DTB write accesses system.switch_cpus03.dtb.data_hits 50 # DTB hits system.switch_cpus03.dtb.data_misses 0 # DTB misses system.switch_cpus03.dtb.data_acv 0 # DTB access violations system.switch_cpus03.dtb.data_accesses 0 # DTB accesses system.switch_cpus03.itb.fetch_hits 0 # ITB hits system.switch_cpus03.itb.fetch_misses 0 # ITB misses system.switch_cpus03.itb.fetch_acv 0 # ITB acv system.switch_cpus03.itb.fetch_accesses 0 # ITB accesses system.switch_cpus03.itb.read_hits 0 # DTB read hits system.switch_cpus03.itb.read_misses 0 # DTB read misses system.switch_cpus03.itb.read_acv 0 # DTB read access violations system.switch_cpus03.itb.read_accesses 0 # DTB read accesses system.switch_cpus03.itb.write_hits 0 # DTB write hits system.switch_cpus03.itb.write_misses 0 # DTB write misses system.switch_cpus03.itb.write_acv 0 # DTB write access violations system.switch_cpus03.itb.write_accesses 0 # DTB write accesses system.switch_cpus03.itb.data_hits 0 # DTB hits system.switch_cpus03.itb.data_misses 0 # DTB misses system.switch_cpus03.itb.data_acv 0 # DTB access violations system.switch_cpus03.itb.data_accesses 0 # DTB accesses system.switch_cpus03.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus03.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus03.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus03.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus03.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus03.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus03.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus03.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus03.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus03.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus03.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus03.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus03.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus03.kern.mode_good::kernel 0 system.switch_cpus03.kern.mode_good::user 0 system.switch_cpus03.kern.mode_good::idle 0 system.switch_cpus03.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus03.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus03.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus03.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus03.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus03.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus03.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus03.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus03.committedInsts 152 # Number of instructions committed system.switch_cpus03.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus03.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus03.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus03.num_func_calls 0 # number of times a function call or return occured system.switch_cpus03.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus03.num_int_insts 101 # number of integer instructions system.switch_cpus03.num_fp_insts 0 # number of float instructions system.switch_cpus03.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus03.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus03.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus03.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus03.num_mem_refs 50 # number of memory refs system.switch_cpus03.num_load_insts 50 # Number of load instructions system.switch_cpus03.num_store_insts 0 # Number of store instructions system.switch_cpus03.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus03.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus03.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus03.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus03.Branches 51 # Number of branches fetched system.switch_cpus03.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus03.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus03.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus03.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus03.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus03.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus03.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus03.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus03.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus03.op_class::total 152 # Class of executed instruction system.switch_cpus04.dtb.fetch_hits 0 # ITB hits system.switch_cpus04.dtb.fetch_misses 0 # ITB misses system.switch_cpus04.dtb.fetch_acv 0 # ITB acv system.switch_cpus04.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus04.dtb.read_hits 50 # DTB read hits system.switch_cpus04.dtb.read_misses 0 # DTB read misses system.switch_cpus04.dtb.read_acv 0 # DTB read access violations system.switch_cpus04.dtb.read_accesses 0 # DTB read accesses system.switch_cpus04.dtb.write_hits 0 # DTB write hits system.switch_cpus04.dtb.write_misses 0 # DTB write misses system.switch_cpus04.dtb.write_acv 0 # DTB write access violations system.switch_cpus04.dtb.write_accesses 0 # DTB write accesses system.switch_cpus04.dtb.data_hits 50 # DTB hits system.switch_cpus04.dtb.data_misses 0 # DTB misses system.switch_cpus04.dtb.data_acv 0 # DTB access violations system.switch_cpus04.dtb.data_accesses 0 # DTB accesses system.switch_cpus04.itb.fetch_hits 0 # ITB hits system.switch_cpus04.itb.fetch_misses 0 # ITB misses system.switch_cpus04.itb.fetch_acv 0 # ITB acv system.switch_cpus04.itb.fetch_accesses 0 # ITB accesses system.switch_cpus04.itb.read_hits 0 # DTB read hits system.switch_cpus04.itb.read_misses 0 # DTB read misses system.switch_cpus04.itb.read_acv 0 # DTB read access violations system.switch_cpus04.itb.read_accesses 0 # DTB read accesses system.switch_cpus04.itb.write_hits 0 # DTB write hits system.switch_cpus04.itb.write_misses 0 # DTB write misses system.switch_cpus04.itb.write_acv 0 # DTB write access violations system.switch_cpus04.itb.write_accesses 0 # DTB write accesses system.switch_cpus04.itb.data_hits 0 # DTB hits system.switch_cpus04.itb.data_misses 0 # DTB misses system.switch_cpus04.itb.data_acv 0 # DTB access violations system.switch_cpus04.itb.data_accesses 0 # DTB accesses system.switch_cpus04.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus04.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus04.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus04.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus04.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus04.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus04.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus04.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus04.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus04.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus04.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus04.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus04.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus04.kern.mode_good::kernel 0 system.switch_cpus04.kern.mode_good::user 0 system.switch_cpus04.kern.mode_good::idle 0 system.switch_cpus04.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus04.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus04.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus04.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus04.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus04.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus04.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus04.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus04.committedInsts 152 # Number of instructions committed system.switch_cpus04.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus04.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus04.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus04.num_func_calls 0 # number of times a function call or return occured system.switch_cpus04.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus04.num_int_insts 101 # number of integer instructions system.switch_cpus04.num_fp_insts 0 # number of float instructions system.switch_cpus04.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus04.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus04.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus04.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus04.num_mem_refs 50 # number of memory refs system.switch_cpus04.num_load_insts 50 # Number of load instructions system.switch_cpus04.num_store_insts 0 # Number of store instructions system.switch_cpus04.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus04.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus04.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus04.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus04.Branches 51 # Number of branches fetched system.switch_cpus04.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus04.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus04.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus04.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus04.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus04.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus04.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus04.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus04.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus04.op_class::total 152 # Class of executed instruction system.switch_cpus05.dtb.fetch_hits 0 # ITB hits system.switch_cpus05.dtb.fetch_misses 0 # ITB misses system.switch_cpus05.dtb.fetch_acv 0 # ITB acv system.switch_cpus05.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus05.dtb.read_hits 50 # DTB read hits system.switch_cpus05.dtb.read_misses 0 # DTB read misses system.switch_cpus05.dtb.read_acv 0 # DTB read access violations system.switch_cpus05.dtb.read_accesses 0 # DTB read accesses system.switch_cpus05.dtb.write_hits 0 # DTB write hits system.switch_cpus05.dtb.write_misses 0 # DTB write misses system.switch_cpus05.dtb.write_acv 0 # DTB write access violations system.switch_cpus05.dtb.write_accesses 0 # DTB write accesses system.switch_cpus05.dtb.data_hits 50 # DTB hits system.switch_cpus05.dtb.data_misses 0 # DTB misses system.switch_cpus05.dtb.data_acv 0 # DTB access violations system.switch_cpus05.dtb.data_accesses 0 # DTB accesses system.switch_cpus05.itb.fetch_hits 0 # ITB hits system.switch_cpus05.itb.fetch_misses 0 # ITB misses system.switch_cpus05.itb.fetch_acv 0 # ITB acv system.switch_cpus05.itb.fetch_accesses 0 # ITB accesses system.switch_cpus05.itb.read_hits 0 # DTB read hits system.switch_cpus05.itb.read_misses 0 # DTB read misses system.switch_cpus05.itb.read_acv 0 # DTB read access violations system.switch_cpus05.itb.read_accesses 0 # DTB read accesses system.switch_cpus05.itb.write_hits 0 # DTB write hits system.switch_cpus05.itb.write_misses 0 # DTB write misses system.switch_cpus05.itb.write_acv 0 # DTB write access violations system.switch_cpus05.itb.write_accesses 0 # DTB write accesses system.switch_cpus05.itb.data_hits 0 # DTB hits system.switch_cpus05.itb.data_misses 0 # DTB misses system.switch_cpus05.itb.data_acv 0 # DTB access violations system.switch_cpus05.itb.data_accesses 0 # DTB accesses system.switch_cpus05.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus05.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus05.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus05.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus05.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus05.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus05.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus05.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus05.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus05.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus05.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus05.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus05.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus05.kern.mode_good::kernel 0 system.switch_cpus05.kern.mode_good::user 0 system.switch_cpus05.kern.mode_good::idle 0 system.switch_cpus05.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus05.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus05.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus05.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus05.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus05.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus05.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus05.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus05.committedInsts 152 # Number of instructions committed system.switch_cpus05.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus05.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus05.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus05.num_func_calls 0 # number of times a function call or return occured system.switch_cpus05.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus05.num_int_insts 101 # number of integer instructions system.switch_cpus05.num_fp_insts 0 # number of float instructions system.switch_cpus05.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus05.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus05.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus05.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus05.num_mem_refs 50 # number of memory refs system.switch_cpus05.num_load_insts 50 # Number of load instructions system.switch_cpus05.num_store_insts 0 # Number of store instructions system.switch_cpus05.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus05.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus05.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus05.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus05.Branches 51 # Number of branches fetched system.switch_cpus05.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus05.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus05.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus05.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus05.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus05.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus05.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus05.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus05.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus05.op_class::total 152 # Class of executed instruction system.switch_cpus06.dtb.fetch_hits 0 # ITB hits system.switch_cpus06.dtb.fetch_misses 0 # ITB misses system.switch_cpus06.dtb.fetch_acv 0 # ITB acv system.switch_cpus06.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus06.dtb.read_hits 50 # DTB read hits system.switch_cpus06.dtb.read_misses 0 # DTB read misses system.switch_cpus06.dtb.read_acv 0 # DTB read access violations system.switch_cpus06.dtb.read_accesses 0 # DTB read accesses system.switch_cpus06.dtb.write_hits 0 # DTB write hits system.switch_cpus06.dtb.write_misses 0 # DTB write misses system.switch_cpus06.dtb.write_acv 0 # DTB write access violations system.switch_cpus06.dtb.write_accesses 0 # DTB write accesses system.switch_cpus06.dtb.data_hits 50 # DTB hits system.switch_cpus06.dtb.data_misses 0 # DTB misses system.switch_cpus06.dtb.data_acv 0 # DTB access violations system.switch_cpus06.dtb.data_accesses 0 # DTB accesses system.switch_cpus06.itb.fetch_hits 0 # ITB hits system.switch_cpus06.itb.fetch_misses 0 # ITB misses system.switch_cpus06.itb.fetch_acv 0 # ITB acv system.switch_cpus06.itb.fetch_accesses 0 # ITB accesses system.switch_cpus06.itb.read_hits 0 # DTB read hits system.switch_cpus06.itb.read_misses 0 # DTB read misses system.switch_cpus06.itb.read_acv 0 # DTB read access violations system.switch_cpus06.itb.read_accesses 0 # DTB read accesses system.switch_cpus06.itb.write_hits 0 # DTB write hits system.switch_cpus06.itb.write_misses 0 # DTB write misses system.switch_cpus06.itb.write_acv 0 # DTB write access violations system.switch_cpus06.itb.write_accesses 0 # DTB write accesses system.switch_cpus06.itb.data_hits 0 # DTB hits system.switch_cpus06.itb.data_misses 0 # DTB misses system.switch_cpus06.itb.data_acv 0 # DTB access violations system.switch_cpus06.itb.data_accesses 0 # DTB accesses system.switch_cpus06.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus06.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus06.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus06.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus06.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus06.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus06.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus06.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus06.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus06.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus06.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus06.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus06.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus06.kern.mode_good::kernel 0 system.switch_cpus06.kern.mode_good::user 0 system.switch_cpus06.kern.mode_good::idle 0 system.switch_cpus06.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus06.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus06.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus06.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus06.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus06.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus06.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus06.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus06.committedInsts 152 # Number of instructions committed system.switch_cpus06.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus06.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus06.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus06.num_func_calls 0 # number of times a function call or return occured system.switch_cpus06.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus06.num_int_insts 101 # number of integer instructions system.switch_cpus06.num_fp_insts 0 # number of float instructions system.switch_cpus06.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus06.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus06.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus06.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus06.num_mem_refs 50 # number of memory refs system.switch_cpus06.num_load_insts 50 # Number of load instructions system.switch_cpus06.num_store_insts 0 # Number of store instructions system.switch_cpus06.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus06.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus06.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus06.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus06.Branches 51 # Number of branches fetched system.switch_cpus06.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus06.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus06.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus06.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus06.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus06.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus06.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus06.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus06.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus06.op_class::total 152 # Class of executed instruction system.switch_cpus07.dtb.fetch_hits 0 # ITB hits system.switch_cpus07.dtb.fetch_misses 0 # ITB misses system.switch_cpus07.dtb.fetch_acv 0 # ITB acv system.switch_cpus07.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus07.dtb.read_hits 50 # DTB read hits system.switch_cpus07.dtb.read_misses 0 # DTB read misses system.switch_cpus07.dtb.read_acv 0 # DTB read access violations system.switch_cpus07.dtb.read_accesses 0 # DTB read accesses system.switch_cpus07.dtb.write_hits 0 # DTB write hits system.switch_cpus07.dtb.write_misses 0 # DTB write misses system.switch_cpus07.dtb.write_acv 0 # DTB write access violations system.switch_cpus07.dtb.write_accesses 0 # DTB write accesses system.switch_cpus07.dtb.data_hits 50 # DTB hits system.switch_cpus07.dtb.data_misses 0 # DTB misses system.switch_cpus07.dtb.data_acv 0 # DTB access violations system.switch_cpus07.dtb.data_accesses 0 # DTB accesses system.switch_cpus07.itb.fetch_hits 0 # ITB hits system.switch_cpus07.itb.fetch_misses 0 # ITB misses system.switch_cpus07.itb.fetch_acv 0 # ITB acv system.switch_cpus07.itb.fetch_accesses 0 # ITB accesses system.switch_cpus07.itb.read_hits 0 # DTB read hits system.switch_cpus07.itb.read_misses 0 # DTB read misses system.switch_cpus07.itb.read_acv 0 # DTB read access violations system.switch_cpus07.itb.read_accesses 0 # DTB read accesses system.switch_cpus07.itb.write_hits 0 # DTB write hits system.switch_cpus07.itb.write_misses 0 # DTB write misses system.switch_cpus07.itb.write_acv 0 # DTB write access violations system.switch_cpus07.itb.write_accesses 0 # DTB write accesses system.switch_cpus07.itb.data_hits 0 # DTB hits system.switch_cpus07.itb.data_misses 0 # DTB misses system.switch_cpus07.itb.data_acv 0 # DTB access violations system.switch_cpus07.itb.data_accesses 0 # DTB accesses system.switch_cpus07.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus07.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus07.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus07.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus07.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus07.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus07.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus07.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus07.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus07.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus07.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus07.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus07.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus07.kern.mode_good::kernel 0 system.switch_cpus07.kern.mode_good::user 0 system.switch_cpus07.kern.mode_good::idle 0 system.switch_cpus07.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus07.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus07.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus07.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus07.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus07.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus07.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus07.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus07.committedInsts 152 # Number of instructions committed system.switch_cpus07.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus07.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus07.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus07.num_func_calls 0 # number of times a function call or return occured system.switch_cpus07.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus07.num_int_insts 101 # number of integer instructions system.switch_cpus07.num_fp_insts 0 # number of float instructions system.switch_cpus07.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus07.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus07.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus07.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus07.num_mem_refs 50 # number of memory refs system.switch_cpus07.num_load_insts 50 # Number of load instructions system.switch_cpus07.num_store_insts 0 # Number of store instructions system.switch_cpus07.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus07.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus07.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus07.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus07.Branches 51 # Number of branches fetched system.switch_cpus07.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus07.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus07.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus07.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus07.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus07.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus07.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus07.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus07.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus07.op_class::total 152 # Class of executed instruction system.switch_cpus08.dtb.fetch_hits 0 # ITB hits system.switch_cpus08.dtb.fetch_misses 0 # ITB misses system.switch_cpus08.dtb.fetch_acv 0 # ITB acv system.switch_cpus08.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus08.dtb.read_hits 50 # DTB read hits system.switch_cpus08.dtb.read_misses 0 # DTB read misses system.switch_cpus08.dtb.read_acv 0 # DTB read access violations system.switch_cpus08.dtb.read_accesses 0 # DTB read accesses system.switch_cpus08.dtb.write_hits 0 # DTB write hits system.switch_cpus08.dtb.write_misses 0 # DTB write misses system.switch_cpus08.dtb.write_acv 0 # DTB write access violations system.switch_cpus08.dtb.write_accesses 0 # DTB write accesses system.switch_cpus08.dtb.data_hits 50 # DTB hits system.switch_cpus08.dtb.data_misses 0 # DTB misses system.switch_cpus08.dtb.data_acv 0 # DTB access violations system.switch_cpus08.dtb.data_accesses 0 # DTB accesses system.switch_cpus08.itb.fetch_hits 0 # ITB hits system.switch_cpus08.itb.fetch_misses 0 # ITB misses system.switch_cpus08.itb.fetch_acv 0 # ITB acv system.switch_cpus08.itb.fetch_accesses 0 # ITB accesses system.switch_cpus08.itb.read_hits 0 # DTB read hits system.switch_cpus08.itb.read_misses 0 # DTB read misses system.switch_cpus08.itb.read_acv 0 # DTB read access violations system.switch_cpus08.itb.read_accesses 0 # DTB read accesses system.switch_cpus08.itb.write_hits 0 # DTB write hits system.switch_cpus08.itb.write_misses 0 # DTB write misses system.switch_cpus08.itb.write_acv 0 # DTB write access violations system.switch_cpus08.itb.write_accesses 0 # DTB write accesses system.switch_cpus08.itb.data_hits 0 # DTB hits system.switch_cpus08.itb.data_misses 0 # DTB misses system.switch_cpus08.itb.data_acv 0 # DTB access violations system.switch_cpus08.itb.data_accesses 0 # DTB accesses system.switch_cpus08.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus08.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus08.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus08.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus08.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus08.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus08.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus08.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus08.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus08.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus08.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus08.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus08.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus08.kern.mode_good::kernel 0 system.switch_cpus08.kern.mode_good::user 0 system.switch_cpus08.kern.mode_good::idle 0 system.switch_cpus08.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus08.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus08.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus08.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus08.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus08.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus08.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus08.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus08.committedInsts 152 # Number of instructions committed system.switch_cpus08.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus08.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus08.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus08.num_func_calls 0 # number of times a function call or return occured system.switch_cpus08.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus08.num_int_insts 101 # number of integer instructions system.switch_cpus08.num_fp_insts 0 # number of float instructions system.switch_cpus08.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus08.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus08.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus08.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus08.num_mem_refs 50 # number of memory refs system.switch_cpus08.num_load_insts 50 # Number of load instructions system.switch_cpus08.num_store_insts 0 # Number of store instructions system.switch_cpus08.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus08.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus08.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus08.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus08.Branches 51 # Number of branches fetched system.switch_cpus08.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus08.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus08.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus08.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus08.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus08.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus08.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus08.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus08.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus08.op_class::total 152 # Class of executed instruction system.switch_cpus09.dtb.fetch_hits 0 # ITB hits system.switch_cpus09.dtb.fetch_misses 0 # ITB misses system.switch_cpus09.dtb.fetch_acv 0 # ITB acv system.switch_cpus09.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus09.dtb.read_hits 50 # DTB read hits system.switch_cpus09.dtb.read_misses 0 # DTB read misses system.switch_cpus09.dtb.read_acv 0 # DTB read access violations system.switch_cpus09.dtb.read_accesses 0 # DTB read accesses system.switch_cpus09.dtb.write_hits 0 # DTB write hits system.switch_cpus09.dtb.write_misses 0 # DTB write misses system.switch_cpus09.dtb.write_acv 0 # DTB write access violations system.switch_cpus09.dtb.write_accesses 0 # DTB write accesses system.switch_cpus09.dtb.data_hits 50 # DTB hits system.switch_cpus09.dtb.data_misses 0 # DTB misses system.switch_cpus09.dtb.data_acv 0 # DTB access violations system.switch_cpus09.dtb.data_accesses 0 # DTB accesses system.switch_cpus09.itb.fetch_hits 0 # ITB hits system.switch_cpus09.itb.fetch_misses 0 # ITB misses system.switch_cpus09.itb.fetch_acv 0 # ITB acv system.switch_cpus09.itb.fetch_accesses 0 # ITB accesses system.switch_cpus09.itb.read_hits 0 # DTB read hits system.switch_cpus09.itb.read_misses 0 # DTB read misses system.switch_cpus09.itb.read_acv 0 # DTB read access violations system.switch_cpus09.itb.read_accesses 0 # DTB read accesses system.switch_cpus09.itb.write_hits 0 # DTB write hits system.switch_cpus09.itb.write_misses 0 # DTB write misses system.switch_cpus09.itb.write_acv 0 # DTB write access violations system.switch_cpus09.itb.write_accesses 0 # DTB write accesses system.switch_cpus09.itb.data_hits 0 # DTB hits system.switch_cpus09.itb.data_misses 0 # DTB misses system.switch_cpus09.itb.data_acv 0 # DTB access violations system.switch_cpus09.itb.data_accesses 0 # DTB accesses system.switch_cpus09.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus09.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus09.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus09.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus09.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus09.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus09.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus09.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus09.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus09.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus09.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus09.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus09.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus09.kern.mode_good::kernel 0 system.switch_cpus09.kern.mode_good::user 0 system.switch_cpus09.kern.mode_good::idle 0 system.switch_cpus09.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus09.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus09.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus09.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus09.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus09.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus09.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus09.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus09.committedInsts 152 # Number of instructions committed system.switch_cpus09.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus09.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus09.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus09.num_func_calls 0 # number of times a function call or return occured system.switch_cpus09.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus09.num_int_insts 101 # number of integer instructions system.switch_cpus09.num_fp_insts 0 # number of float instructions system.switch_cpus09.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus09.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus09.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus09.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus09.num_mem_refs 50 # number of memory refs system.switch_cpus09.num_load_insts 50 # Number of load instructions system.switch_cpus09.num_store_insts 0 # Number of store instructions system.switch_cpus09.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus09.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus09.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus09.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus09.Branches 51 # Number of branches fetched system.switch_cpus09.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus09.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus09.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus09.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus09.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus09.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus09.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus09.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus09.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus09.op_class::total 152 # Class of executed instruction system.switch_cpus10.dtb.fetch_hits 0 # ITB hits system.switch_cpus10.dtb.fetch_misses 0 # ITB misses system.switch_cpus10.dtb.fetch_acv 0 # ITB acv system.switch_cpus10.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus10.dtb.read_hits 50 # DTB read hits system.switch_cpus10.dtb.read_misses 0 # DTB read misses system.switch_cpus10.dtb.read_acv 0 # DTB read access violations system.switch_cpus10.dtb.read_accesses 0 # DTB read accesses system.switch_cpus10.dtb.write_hits 0 # DTB write hits system.switch_cpus10.dtb.write_misses 0 # DTB write misses system.switch_cpus10.dtb.write_acv 0 # DTB write access violations system.switch_cpus10.dtb.write_accesses 0 # DTB write accesses system.switch_cpus10.dtb.data_hits 50 # DTB hits system.switch_cpus10.dtb.data_misses 0 # DTB misses system.switch_cpus10.dtb.data_acv 0 # DTB access violations system.switch_cpus10.dtb.data_accesses 0 # DTB accesses system.switch_cpus10.itb.fetch_hits 0 # ITB hits system.switch_cpus10.itb.fetch_misses 0 # ITB misses system.switch_cpus10.itb.fetch_acv 0 # ITB acv system.switch_cpus10.itb.fetch_accesses 0 # ITB accesses system.switch_cpus10.itb.read_hits 0 # DTB read hits system.switch_cpus10.itb.read_misses 0 # DTB read misses system.switch_cpus10.itb.read_acv 0 # DTB read access violations system.switch_cpus10.itb.read_accesses 0 # DTB read accesses system.switch_cpus10.itb.write_hits 0 # DTB write hits system.switch_cpus10.itb.write_misses 0 # DTB write misses system.switch_cpus10.itb.write_acv 0 # DTB write access violations system.switch_cpus10.itb.write_accesses 0 # DTB write accesses system.switch_cpus10.itb.data_hits 0 # DTB hits system.switch_cpus10.itb.data_misses 0 # DTB misses system.switch_cpus10.itb.data_acv 0 # DTB access violations system.switch_cpus10.itb.data_accesses 0 # DTB accesses system.switch_cpus10.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus10.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus10.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus10.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus10.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus10.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus10.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus10.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus10.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus10.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus10.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus10.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus10.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus10.kern.mode_good::kernel 0 system.switch_cpus10.kern.mode_good::user 0 system.switch_cpus10.kern.mode_good::idle 0 system.switch_cpus10.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus10.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus10.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus10.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus10.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus10.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus10.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus10.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus10.committedInsts 152 # Number of instructions committed system.switch_cpus10.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus10.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus10.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus10.num_func_calls 0 # number of times a function call or return occured system.switch_cpus10.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus10.num_int_insts 101 # number of integer instructions system.switch_cpus10.num_fp_insts 0 # number of float instructions system.switch_cpus10.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus10.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus10.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus10.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus10.num_mem_refs 50 # number of memory refs system.switch_cpus10.num_load_insts 50 # Number of load instructions system.switch_cpus10.num_store_insts 0 # Number of store instructions system.switch_cpus10.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus10.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus10.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus10.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus10.Branches 51 # Number of branches fetched system.switch_cpus10.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus10.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus10.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus10.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus10.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus10.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus10.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus10.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus10.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus10.op_class::total 152 # Class of executed instruction system.switch_cpus11.dtb.fetch_hits 0 # ITB hits system.switch_cpus11.dtb.fetch_misses 0 # ITB misses system.switch_cpus11.dtb.fetch_acv 0 # ITB acv system.switch_cpus11.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus11.dtb.read_hits 50 # DTB read hits system.switch_cpus11.dtb.read_misses 0 # DTB read misses system.switch_cpus11.dtb.read_acv 0 # DTB read access violations system.switch_cpus11.dtb.read_accesses 0 # DTB read accesses system.switch_cpus11.dtb.write_hits 0 # DTB write hits system.switch_cpus11.dtb.write_misses 0 # DTB write misses system.switch_cpus11.dtb.write_acv 0 # DTB write access violations system.switch_cpus11.dtb.write_accesses 0 # DTB write accesses system.switch_cpus11.dtb.data_hits 50 # DTB hits system.switch_cpus11.dtb.data_misses 0 # DTB misses system.switch_cpus11.dtb.data_acv 0 # DTB access violations system.switch_cpus11.dtb.data_accesses 0 # DTB accesses system.switch_cpus11.itb.fetch_hits 0 # ITB hits system.switch_cpus11.itb.fetch_misses 0 # ITB misses system.switch_cpus11.itb.fetch_acv 0 # ITB acv system.switch_cpus11.itb.fetch_accesses 0 # ITB accesses system.switch_cpus11.itb.read_hits 0 # DTB read hits system.switch_cpus11.itb.read_misses 0 # DTB read misses system.switch_cpus11.itb.read_acv 0 # DTB read access violations system.switch_cpus11.itb.read_accesses 0 # DTB read accesses system.switch_cpus11.itb.write_hits 0 # DTB write hits system.switch_cpus11.itb.write_misses 0 # DTB write misses system.switch_cpus11.itb.write_acv 0 # DTB write access violations system.switch_cpus11.itb.write_accesses 0 # DTB write accesses system.switch_cpus11.itb.data_hits 0 # DTB hits system.switch_cpus11.itb.data_misses 0 # DTB misses system.switch_cpus11.itb.data_acv 0 # DTB access violations system.switch_cpus11.itb.data_accesses 0 # DTB accesses system.switch_cpus11.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus11.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus11.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus11.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus11.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus11.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus11.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus11.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus11.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus11.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus11.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus11.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus11.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus11.kern.mode_good::kernel 0 system.switch_cpus11.kern.mode_good::user 0 system.switch_cpus11.kern.mode_good::idle 0 system.switch_cpus11.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus11.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus11.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus11.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus11.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus11.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus11.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus11.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus11.committedInsts 152 # Number of instructions committed system.switch_cpus11.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus11.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus11.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus11.num_func_calls 0 # number of times a function call or return occured system.switch_cpus11.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus11.num_int_insts 101 # number of integer instructions system.switch_cpus11.num_fp_insts 0 # number of float instructions system.switch_cpus11.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus11.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus11.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus11.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus11.num_mem_refs 50 # number of memory refs system.switch_cpus11.num_load_insts 50 # Number of load instructions system.switch_cpus11.num_store_insts 0 # Number of store instructions system.switch_cpus11.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus11.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus11.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus11.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus11.Branches 51 # Number of branches fetched system.switch_cpus11.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus11.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus11.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus11.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus11.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus11.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus11.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus11.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus11.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus11.op_class::total 152 # Class of executed instruction system.switch_cpus12.dtb.fetch_hits 0 # ITB hits system.switch_cpus12.dtb.fetch_misses 0 # ITB misses system.switch_cpus12.dtb.fetch_acv 0 # ITB acv system.switch_cpus12.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus12.dtb.read_hits 50 # DTB read hits system.switch_cpus12.dtb.read_misses 0 # DTB read misses system.switch_cpus12.dtb.read_acv 0 # DTB read access violations system.switch_cpus12.dtb.read_accesses 0 # DTB read accesses system.switch_cpus12.dtb.write_hits 0 # DTB write hits system.switch_cpus12.dtb.write_misses 0 # DTB write misses system.switch_cpus12.dtb.write_acv 0 # DTB write access violations system.switch_cpus12.dtb.write_accesses 0 # DTB write accesses system.switch_cpus12.dtb.data_hits 50 # DTB hits system.switch_cpus12.dtb.data_misses 0 # DTB misses system.switch_cpus12.dtb.data_acv 0 # DTB access violations system.switch_cpus12.dtb.data_accesses 0 # DTB accesses system.switch_cpus12.itb.fetch_hits 0 # ITB hits system.switch_cpus12.itb.fetch_misses 0 # ITB misses system.switch_cpus12.itb.fetch_acv 0 # ITB acv system.switch_cpus12.itb.fetch_accesses 0 # ITB accesses system.switch_cpus12.itb.read_hits 0 # DTB read hits system.switch_cpus12.itb.read_misses 0 # DTB read misses system.switch_cpus12.itb.read_acv 0 # DTB read access violations system.switch_cpus12.itb.read_accesses 0 # DTB read accesses system.switch_cpus12.itb.write_hits 0 # DTB write hits system.switch_cpus12.itb.write_misses 0 # DTB write misses system.switch_cpus12.itb.write_acv 0 # DTB write access violations system.switch_cpus12.itb.write_accesses 0 # DTB write accesses system.switch_cpus12.itb.data_hits 0 # DTB hits system.switch_cpus12.itb.data_misses 0 # DTB misses system.switch_cpus12.itb.data_acv 0 # DTB access violations system.switch_cpus12.itb.data_accesses 0 # DTB accesses system.switch_cpus12.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus12.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus12.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus12.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus12.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus12.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus12.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus12.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus12.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus12.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus12.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus12.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus12.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus12.kern.mode_good::kernel 0 system.switch_cpus12.kern.mode_good::user 0 system.switch_cpus12.kern.mode_good::idle 0 system.switch_cpus12.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus12.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus12.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus12.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus12.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus12.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus12.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus12.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus12.committedInsts 152 # Number of instructions committed system.switch_cpus12.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus12.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus12.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus12.num_func_calls 0 # number of times a function call or return occured system.switch_cpus12.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus12.num_int_insts 101 # number of integer instructions system.switch_cpus12.num_fp_insts 0 # number of float instructions system.switch_cpus12.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus12.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus12.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus12.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus12.num_mem_refs 50 # number of memory refs system.switch_cpus12.num_load_insts 50 # Number of load instructions system.switch_cpus12.num_store_insts 0 # Number of store instructions system.switch_cpus12.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus12.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus12.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus12.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus12.Branches 51 # Number of branches fetched system.switch_cpus12.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus12.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus12.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus12.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus12.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus12.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus12.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus12.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus12.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus12.op_class::total 152 # Class of executed instruction system.switch_cpus13.dtb.fetch_hits 0 # ITB hits system.switch_cpus13.dtb.fetch_misses 0 # ITB misses system.switch_cpus13.dtb.fetch_acv 0 # ITB acv system.switch_cpus13.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus13.dtb.read_hits 50 # DTB read hits system.switch_cpus13.dtb.read_misses 0 # DTB read misses system.switch_cpus13.dtb.read_acv 0 # DTB read access violations system.switch_cpus13.dtb.read_accesses 0 # DTB read accesses system.switch_cpus13.dtb.write_hits 0 # DTB write hits system.switch_cpus13.dtb.write_misses 0 # DTB write misses system.switch_cpus13.dtb.write_acv 0 # DTB write access violations system.switch_cpus13.dtb.write_accesses 0 # DTB write accesses system.switch_cpus13.dtb.data_hits 50 # DTB hits system.switch_cpus13.dtb.data_misses 0 # DTB misses system.switch_cpus13.dtb.data_acv 0 # DTB access violations system.switch_cpus13.dtb.data_accesses 0 # DTB accesses system.switch_cpus13.itb.fetch_hits 0 # ITB hits system.switch_cpus13.itb.fetch_misses 0 # ITB misses system.switch_cpus13.itb.fetch_acv 0 # ITB acv system.switch_cpus13.itb.fetch_accesses 0 # ITB accesses system.switch_cpus13.itb.read_hits 0 # DTB read hits system.switch_cpus13.itb.read_misses 0 # DTB read misses system.switch_cpus13.itb.read_acv 0 # DTB read access violations system.switch_cpus13.itb.read_accesses 0 # DTB read accesses system.switch_cpus13.itb.write_hits 0 # DTB write hits system.switch_cpus13.itb.write_misses 0 # DTB write misses system.switch_cpus13.itb.write_acv 0 # DTB write access violations system.switch_cpus13.itb.write_accesses 0 # DTB write accesses system.switch_cpus13.itb.data_hits 0 # DTB hits system.switch_cpus13.itb.data_misses 0 # DTB misses system.switch_cpus13.itb.data_acv 0 # DTB access violations system.switch_cpus13.itb.data_accesses 0 # DTB accesses system.switch_cpus13.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus13.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus13.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus13.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus13.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus13.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus13.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus13.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus13.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus13.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus13.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus13.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus13.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus13.kern.mode_good::kernel 0 system.switch_cpus13.kern.mode_good::user 0 system.switch_cpus13.kern.mode_good::idle 0 system.switch_cpus13.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus13.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus13.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus13.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus13.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus13.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus13.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus13.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus13.committedInsts 152 # Number of instructions committed system.switch_cpus13.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus13.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus13.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus13.num_func_calls 0 # number of times a function call or return occured system.switch_cpus13.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus13.num_int_insts 101 # number of integer instructions system.switch_cpus13.num_fp_insts 0 # number of float instructions system.switch_cpus13.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus13.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus13.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus13.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus13.num_mem_refs 50 # number of memory refs system.switch_cpus13.num_load_insts 50 # Number of load instructions system.switch_cpus13.num_store_insts 0 # Number of store instructions system.switch_cpus13.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus13.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus13.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus13.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus13.Branches 51 # Number of branches fetched system.switch_cpus13.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus13.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus13.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus13.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus13.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus13.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus13.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus13.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus13.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus13.op_class::total 152 # Class of executed instruction system.switch_cpus14.dtb.fetch_hits 0 # ITB hits system.switch_cpus14.dtb.fetch_misses 0 # ITB misses system.switch_cpus14.dtb.fetch_acv 0 # ITB acv system.switch_cpus14.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus14.dtb.read_hits 50 # DTB read hits system.switch_cpus14.dtb.read_misses 0 # DTB read misses system.switch_cpus14.dtb.read_acv 0 # DTB read access violations system.switch_cpus14.dtb.read_accesses 0 # DTB read accesses system.switch_cpus14.dtb.write_hits 0 # DTB write hits system.switch_cpus14.dtb.write_misses 0 # DTB write misses system.switch_cpus14.dtb.write_acv 0 # DTB write access violations system.switch_cpus14.dtb.write_accesses 0 # DTB write accesses system.switch_cpus14.dtb.data_hits 50 # DTB hits system.switch_cpus14.dtb.data_misses 0 # DTB misses system.switch_cpus14.dtb.data_acv 0 # DTB access violations system.switch_cpus14.dtb.data_accesses 0 # DTB accesses system.switch_cpus14.itb.fetch_hits 0 # ITB hits system.switch_cpus14.itb.fetch_misses 0 # ITB misses system.switch_cpus14.itb.fetch_acv 0 # ITB acv system.switch_cpus14.itb.fetch_accesses 0 # ITB accesses system.switch_cpus14.itb.read_hits 0 # DTB read hits system.switch_cpus14.itb.read_misses 0 # DTB read misses system.switch_cpus14.itb.read_acv 0 # DTB read access violations system.switch_cpus14.itb.read_accesses 0 # DTB read accesses system.switch_cpus14.itb.write_hits 0 # DTB write hits system.switch_cpus14.itb.write_misses 0 # DTB write misses system.switch_cpus14.itb.write_acv 0 # DTB write access violations system.switch_cpus14.itb.write_accesses 0 # DTB write accesses system.switch_cpus14.itb.data_hits 0 # DTB hits system.switch_cpus14.itb.data_misses 0 # DTB misses system.switch_cpus14.itb.data_acv 0 # DTB access violations system.switch_cpus14.itb.data_accesses 0 # DTB accesses system.switch_cpus14.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus14.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus14.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus14.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus14.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus14.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus14.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus14.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus14.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus14.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus14.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus14.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus14.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus14.kern.mode_good::kernel 0 system.switch_cpus14.kern.mode_good::user 0 system.switch_cpus14.kern.mode_good::idle 0 system.switch_cpus14.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus14.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus14.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus14.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus14.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus14.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus14.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus14.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus14.committedInsts 152 # Number of instructions committed system.switch_cpus14.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus14.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus14.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus14.num_func_calls 0 # number of times a function call or return occured system.switch_cpus14.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus14.num_int_insts 101 # number of integer instructions system.switch_cpus14.num_fp_insts 0 # number of float instructions system.switch_cpus14.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus14.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus14.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus14.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus14.num_mem_refs 50 # number of memory refs system.switch_cpus14.num_load_insts 50 # Number of load instructions system.switch_cpus14.num_store_insts 0 # Number of store instructions system.switch_cpus14.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus14.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus14.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus14.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus14.Branches 51 # Number of branches fetched system.switch_cpus14.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus14.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus14.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus14.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus14.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus14.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus14.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus14.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus14.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus14.op_class::total 152 # Class of executed instruction system.switch_cpus15.dtb.fetch_hits 0 # ITB hits system.switch_cpus15.dtb.fetch_misses 0 # ITB misses system.switch_cpus15.dtb.fetch_acv 0 # ITB acv system.switch_cpus15.dtb.fetch_accesses 0 # ITB accesses system.switch_cpus15.dtb.read_hits 50 # DTB read hits system.switch_cpus15.dtb.read_misses 0 # DTB read misses system.switch_cpus15.dtb.read_acv 0 # DTB read access violations system.switch_cpus15.dtb.read_accesses 0 # DTB read accesses system.switch_cpus15.dtb.write_hits 0 # DTB write hits system.switch_cpus15.dtb.write_misses 0 # DTB write misses system.switch_cpus15.dtb.write_acv 0 # DTB write access violations system.switch_cpus15.dtb.write_accesses 0 # DTB write accesses system.switch_cpus15.dtb.data_hits 50 # DTB hits system.switch_cpus15.dtb.data_misses 0 # DTB misses system.switch_cpus15.dtb.data_acv 0 # DTB access violations system.switch_cpus15.dtb.data_accesses 0 # DTB accesses system.switch_cpus15.itb.fetch_hits 0 # ITB hits system.switch_cpus15.itb.fetch_misses 0 # ITB misses system.switch_cpus15.itb.fetch_acv 0 # ITB acv system.switch_cpus15.itb.fetch_accesses 0 # ITB accesses system.switch_cpus15.itb.read_hits 0 # DTB read hits system.switch_cpus15.itb.read_misses 0 # DTB read misses system.switch_cpus15.itb.read_acv 0 # DTB read access violations system.switch_cpus15.itb.read_accesses 0 # DTB read accesses system.switch_cpus15.itb.write_hits 0 # DTB write hits system.switch_cpus15.itb.write_misses 0 # DTB write misses system.switch_cpus15.itb.write_acv 0 # DTB write access violations system.switch_cpus15.itb.write_accesses 0 # DTB write accesses system.switch_cpus15.itb.data_hits 0 # DTB hits system.switch_cpus15.itb.data_misses 0 # DTB misses system.switch_cpus15.itb.data_acv 0 # DTB access violations system.switch_cpus15.itb.data_accesses 0 # DTB accesses system.switch_cpus15.numPwrStateTransitions 101 # Number of power state transitions system.switch_cpus15.pwrStateClkGateDist::samples 51 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::mean 195613931.372549 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::stdev 7099069.956001 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::1000-5e+10 51 100.00% 100.00% # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::min_value 145910500 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::max_value 196608000 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateClkGateDist::total 51 # Distribution of time spent in the clock gated state system.switch_cpus15.pwrStateResidencyTicks::ON 23689500 # Cumulative time (in ticks) in various power states system.switch_cpus15.pwrStateResidencyTicks::CLK_GATED 9976310500 # Cumulative time (in ticks) in various power states system.switch_cpus15.numCycles 19660952 # number of cpu cycles simulated system.switch_cpus15.numWorkItemsStarted 0 # number of work items this cpu started system.switch_cpus15.numWorkItemsCompleted 0 # number of work items this cpu completed system.switch_cpus15.kern.inst.arm 0 # number of arm instructions executed system.switch_cpus15.kern.inst.quiesce 0 # number of quiesce instructions executed system.switch_cpus15.kern.inst.hwrei 0 # number of hwrei instructions executed system.switch_cpus15.kern.mode_switch::kernel 0 # number of protection mode switches system.switch_cpus15.kern.mode_switch::user 0 # number of protection mode switches system.switch_cpus15.kern.mode_switch::idle 0 # number of protection mode switches system.switch_cpus15.kern.mode_good::kernel 0 system.switch_cpus15.kern.mode_good::user 0 system.switch_cpus15.kern.mode_good::idle 0 system.switch_cpus15.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.switch_cpus15.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.switch_cpus15.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.switch_cpus15.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.switch_cpus15.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.switch_cpus15.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.switch_cpus15.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.switch_cpus15.kern.swap_context 0 # number of times the context was actually changed system.switch_cpus15.committedInsts 152 # Number of instructions committed system.switch_cpus15.committedOps 152 # Number of ops (including micro ops) committed system.switch_cpus15.num_int_alu_accesses 101 # Number of integer alu accesses system.switch_cpus15.num_fp_alu_accesses 0 # Number of float alu accesses system.switch_cpus15.num_func_calls 0 # number of times a function call or return occured system.switch_cpus15.num_conditional_control_insts 51 # number of instructions that are conditional controls system.switch_cpus15.num_int_insts 101 # number of integer instructions system.switch_cpus15.num_fp_insts 0 # number of float instructions system.switch_cpus15.num_int_register_reads 152 # number of times the integer registers were read system.switch_cpus15.num_int_register_writes 50 # number of times the integer registers were written system.switch_cpus15.num_fp_register_reads 0 # number of times the floating registers were read system.switch_cpus15.num_fp_register_writes 0 # number of times the floating registers were written system.switch_cpus15.num_mem_refs 50 # number of memory refs system.switch_cpus15.num_load_insts 50 # Number of load instructions system.switch_cpus15.num_store_insts 0 # Number of store instructions system.switch_cpus15.num_idle_cycles 19660851.729145 # Number of idle cycles system.switch_cpus15.num_busy_cycles 100.270855 # Number of busy cycles system.switch_cpus15.not_idle_fraction 0.000005 # Percentage of non-idle cycles system.switch_cpus15.idle_fraction 0.999995 # Percentage of idle cycles system.switch_cpus15.Branches 51 # Number of branches fetched system.switch_cpus15.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.switch_cpus15.op_class::IntAlu 102 67.11% 67.11% # Class of executed instruction system.switch_cpus15.op_class::IntMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::IntDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::FloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdAddAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdShift 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdShiftAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatAdd 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatAlu 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatCmp 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatCvt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatDiv 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatMisc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatMult 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatMultAcc 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::SimdFloatSqrt 0 0.00% 67.11% # Class of executed instruction system.switch_cpus15.op_class::MemRead 50 32.89% 100.00% # Class of executed instruction system.switch_cpus15.op_class::MemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus15.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.switch_cpus15.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.switch_cpus15.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.switch_cpus15.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.switch_cpus15.op_class::total 152 # Class of executed instruction system.tol2bus.snoop_filter.tot_requests 513380 # Total number of requests made to the snoop filter. system.tol2bus.snoop_filter.hit_single_requests 256155 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.tol2bus.snoop_filter.hit_multi_requests 41 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.tol2bus.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tol2bus.trans_dist::ReadReq 943 # Transaction distribution system.tol2bus.trans_dist::ReadResp 166431 # Transaction distribution system.tol2bus.trans_dist::WriteReq 987 # Transaction distribution system.tol2bus.trans_dist::WriteResp 987 # Transaction distribution system.tol2bus.trans_dist::WritebackDirty 252639 # Transaction distribution system.tol2bus.trans_dist::WritebackClean 578 # Transaction distribution system.tol2bus.trans_dist::CleanEvict 2935 # Transaction distribution system.tol2bus.trans_dist::ReadExReq 91737 # Transaction distribution system.tol2bus.trans_dist::ReadExResp 91737 # Transaction distribution system.tol2bus.trans_dist::ReadCleanReq 1109 # Transaction distribution system.tol2bus.trans_dist::ReadSharedReq 164379 # Transaction distribution system.tol2bus.pkt_count_system.cpu00.icache.mem_side::system.l2.cpu_side 2736 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu00.dcache.mem_side::system.l2.cpu_side 771606 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu01.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu01.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu02.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu02.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu03.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu03.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu04.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu04.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu05.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu05.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu06.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu06.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu07.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu07.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu08.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu08.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu09.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu09.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu10.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu10.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu11.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu11.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu12.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu12.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu13.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu13.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu14.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu14.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu15.icache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count_system.cpu15.dcache.mem_side::system.l2.cpu_side 4 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_count::total 774462 # Packet count per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu00.icache.mem_side::system.l2.cpu_side 106048 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu00.dcache.mem_side::system.l2.cpu_side 32560498 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu01.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu01.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu02.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu02.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu03.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu03.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu04.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu04.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu05.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu05.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu06.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu06.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu07.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu07.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu08.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu08.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu09.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu09.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu10.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu10.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu11.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu11.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu12.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu12.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu13.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu13.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu14.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu14.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu15.icache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size_system.cpu15.dcache.mem_side::system.l2.cpu_side 128 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.pkt_size::total 32670386 # Cumulative packet size per connected master and slave (bytes) system.tol2bus.snoops 0 # Total snoops (count) system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) system.tol2bus.snoop_fanout::samples 515310 # Request fanout histogram system.tol2bus.snoop_fanout::mean 0.000658 # Request fanout histogram system.tol2bus.snoop_fanout::stdev 0.080421 # Request fanout histogram system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.tol2bus.snoop_fanout::0 515266 99.99% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::1 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::2 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::3 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::4 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::5 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::6 3 0.00% 99.99% # Request fanout histogram system.tol2bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::8 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::9 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::10 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::11 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::12 5 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::13 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::14 3 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::15 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::16 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::17 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::18 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::19 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::20 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::21 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::22 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::23 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::24 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::25 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::26 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::27 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::28 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::29 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::30 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::31 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::32 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram system.tol2bus.snoop_fanout::max_value 14 # Request fanout histogram system.tol2bus.snoop_fanout::total 515310 # Request fanout histogram system.tol2bus.reqLayer0.occupancy 34497 # Layer occupancy (ticks) system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer0.occupancy 3000 # Layer occupancy (ticks) system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer1.occupancy 1500 # Layer occupancy (ticks) system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer2.occupancy 3499 # Layer occupancy (ticks) system.tol2bus.respLayer2.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer3.occupancy 3499 # Layer occupancy (ticks) system.tol2bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer4.occupancy 3000 # Layer occupancy (ticks) system.tol2bus.respLayer4.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer5.occupancy 3000 # Layer occupancy (ticks) system.tol2bus.respLayer5.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer6.occupancy 3001 # Layer occupancy (ticks) system.tol2bus.respLayer6.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer7.occupancy 3001 # Layer occupancy (ticks) system.tol2bus.respLayer7.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer8.occupancy 3978 # Layer occupancy (ticks) system.tol2bus.respLayer8.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer9.occupancy 3499 # Layer occupancy (ticks) system.tol2bus.respLayer9.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer10.occupancy 3980 # Layer occupancy (ticks) system.tol2bus.respLayer10.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer11.occupancy 3498 # Layer occupancy (ticks) system.tol2bus.respLayer11.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer12.occupancy 3982 # Layer occupancy (ticks) system.tol2bus.respLayer12.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer13.occupancy 3497 # Layer occupancy (ticks) system.tol2bus.respLayer13.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer14.occupancy 3984 # Layer occupancy (ticks) system.tol2bus.respLayer14.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer15.occupancy 3496 # Layer occupancy (ticks) system.tol2bus.respLayer15.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer16.occupancy 3986 # Layer occupancy (ticks) system.tol2bus.respLayer16.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer17.occupancy 3495 # Layer occupancy (ticks) system.tol2bus.respLayer17.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer18.occupancy 3988 # Layer occupancy (ticks) system.tol2bus.respLayer18.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer19.occupancy 3494 # Layer occupancy (ticks) system.tol2bus.respLayer19.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer20.occupancy 3990 # Layer occupancy (ticks) system.tol2bus.respLayer20.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer21.occupancy 3493 # Layer occupancy (ticks) system.tol2bus.respLayer21.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer22.occupancy 3992 # Layer occupancy (ticks) system.tol2bus.respLayer22.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer23.occupancy 3492 # Layer occupancy (ticks) system.tol2bus.respLayer23.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer24.occupancy 3994 # Layer occupancy (ticks) system.tol2bus.respLayer24.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer25.occupancy 3491 # Layer occupancy (ticks) system.tol2bus.respLayer25.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer26.occupancy 3996 # Layer occupancy (ticks) system.tol2bus.respLayer26.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer27.occupancy 3490 # Layer occupancy (ticks) system.tol2bus.respLayer27.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer28.occupancy 3998 # Layer occupancy (ticks) system.tol2bus.respLayer28.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer29.occupancy 3489 # Layer occupancy (ticks) system.tol2bus.respLayer29.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer30.occupancy 3000 # Layer occupancy (ticks) system.tol2bus.respLayer30.utilization 0.0 # Layer utilization (%) system.tol2bus.respLayer31.occupancy 3000 # Layer occupancy (ticks) system.tol2bus.respLayer31.utilization 0.0 # Layer utilization (%) system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states system.cpu00.kern.inst.arm 0 # number of arm instructions executed system.cpu00.kern.inst.quiesce 918 # number of quiesce instructions executed system.cpu00.kern.inst.hwrei 4495 # number of hwrei instructions executed system.cpu00.kern.ipl_count::0 2152 48.07% 48.07% # number of times we switched to this ipl system.cpu00.kern.ipl_count::22 8 0.18% 48.25% # number of times we switched to this ipl system.cpu00.kern.ipl_count::31 2317 51.75% 100.00% # number of times we switched to this ipl system.cpu00.kern.ipl_count::total 4477 # number of times we switched to this ipl system.cpu00.kern.ipl_good::0 2152 49.92% 49.92% # number of times we switched to this ipl from a different ipl system.cpu00.kern.ipl_good::22 8 0.19% 50.10% # number of times we switched to this ipl from a different ipl system.cpu00.kern.ipl_good::31 2151 49.90% 100.00% # number of times we switched to this ipl from a different ipl system.cpu00.kern.ipl_good::total 4311 # number of times we switched to this ipl from a different ipl system.cpu00.kern.ipl_ticks::0 5298436500 27.13% 27.13% # number of cycles we spent at this ipl system.cpu00.kern.ipl_ticks::22 392000 0.00% 27.13% # number of cycles we spent at this ipl system.cpu00.kern.ipl_ticks::31 14232831500 72.87% 100.00% # number of cycles we spent at this ipl system.cpu00.kern.ipl_ticks::total 19531660000 # number of cycles we spent at this ipl system.cpu00.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl system.cpu00.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu00.kern.ipl_used::31 0.928356 # fraction of swpipl calls that actually changed the ipl system.cpu00.kern.ipl_used::total 0.962922 # fraction of swpipl calls that actually changed the ipl system.cpu00.kern.callpal::wrent 7 0.16% 0.16% # number of callpals executed system.cpu00.kern.callpal::swpipl 4461 99.42% 99.58% # number of callpals executed system.cpu00.kern.callpal::rdps 10 0.22% 99.80% # number of callpals executed system.cpu00.kern.callpal::wrkgp 1 0.02% 99.82% # number of callpals executed system.cpu00.kern.callpal::rti 8 0.18% 100.00% # number of callpals executed system.cpu00.kern.callpal::total 4487 # number of callpals executed system.cpu00.kern.mode_switch::kernel 8 # number of protection mode switches system.cpu00.kern.mode_switch::user 0 # number of protection mode switches system.cpu00.kern.mode_switch::idle 0 # number of protection mode switches system.cpu00.kern.mode_good::kernel 0 system.cpu00.kern.mode_good::user 0 system.cpu00.kern.mode_good::idle 0 system.cpu00.kern.mode_switch_good::kernel 0 # fraction of useful protection mode switches system.cpu00.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu00.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu00.kern.mode_switch_good::total 0 # fraction of useful protection mode switches system.cpu00.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu00.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu00.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu00.kern.swap_context 0 # number of times the context was actually changed system.cpu01.kern.inst.arm 0 # number of arm instructions executed system.cpu01.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu01.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu01.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu01.kern.mode_switch::user 0 # number of protection mode switches system.cpu01.kern.mode_switch::idle 0 # number of protection mode switches system.cpu01.kern.mode_good::kernel 0 system.cpu01.kern.mode_good::user 0 system.cpu01.kern.mode_good::idle 0 system.cpu01.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu01.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu01.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu01.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu01.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu01.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu01.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu01.kern.swap_context 0 # number of times the context was actually changed system.cpu02.kern.inst.arm 0 # number of arm instructions executed system.cpu02.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu02.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu02.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu02.kern.mode_switch::user 0 # number of protection mode switches system.cpu02.kern.mode_switch::idle 0 # number of protection mode switches system.cpu02.kern.mode_good::kernel 0 system.cpu02.kern.mode_good::user 0 system.cpu02.kern.mode_good::idle 0 system.cpu02.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu02.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu02.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu02.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu02.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu02.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu02.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu02.kern.swap_context 0 # number of times the context was actually changed system.cpu03.kern.inst.arm 0 # number of arm instructions executed system.cpu03.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu03.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu03.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu03.kern.mode_switch::user 0 # number of protection mode switches system.cpu03.kern.mode_switch::idle 0 # number of protection mode switches system.cpu03.kern.mode_good::kernel 0 system.cpu03.kern.mode_good::user 0 system.cpu03.kern.mode_good::idle 0 system.cpu03.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu03.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu03.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu03.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu03.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu03.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu03.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu03.kern.swap_context 0 # number of times the context was actually changed system.cpu04.kern.inst.arm 0 # number of arm instructions executed system.cpu04.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu04.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu04.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu04.kern.mode_switch::user 0 # number of protection mode switches system.cpu04.kern.mode_switch::idle 0 # number of protection mode switches system.cpu04.kern.mode_good::kernel 0 system.cpu04.kern.mode_good::user 0 system.cpu04.kern.mode_good::idle 0 system.cpu04.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu04.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu04.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu04.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu04.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu04.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu04.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu04.kern.swap_context 0 # number of times the context was actually changed system.cpu05.kern.inst.arm 0 # number of arm instructions executed system.cpu05.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu05.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu05.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu05.kern.mode_switch::user 0 # number of protection mode switches system.cpu05.kern.mode_switch::idle 0 # number of protection mode switches system.cpu05.kern.mode_good::kernel 0 system.cpu05.kern.mode_good::user 0 system.cpu05.kern.mode_good::idle 0 system.cpu05.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu05.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu05.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu05.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu05.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu05.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu05.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu05.kern.swap_context 0 # number of times the context was actually changed system.cpu06.kern.inst.arm 0 # number of arm instructions executed system.cpu06.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu06.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu06.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu06.kern.mode_switch::user 0 # number of protection mode switches system.cpu06.kern.mode_switch::idle 0 # number of protection mode switches system.cpu06.kern.mode_good::kernel 0 system.cpu06.kern.mode_good::user 0 system.cpu06.kern.mode_good::idle 0 system.cpu06.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu06.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu06.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu06.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu06.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu06.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu06.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu06.kern.swap_context 0 # number of times the context was actually changed system.cpu07.kern.inst.arm 0 # number of arm instructions executed system.cpu07.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu07.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu07.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu07.kern.mode_switch::user 0 # number of protection mode switches system.cpu07.kern.mode_switch::idle 0 # number of protection mode switches system.cpu07.kern.mode_good::kernel 0 system.cpu07.kern.mode_good::user 0 system.cpu07.kern.mode_good::idle 0 system.cpu07.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu07.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu07.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu07.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu07.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu07.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu07.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu07.kern.swap_context 0 # number of times the context was actually changed system.cpu08.kern.inst.arm 0 # number of arm instructions executed system.cpu08.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu08.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu08.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu08.kern.mode_switch::user 0 # number of protection mode switches system.cpu08.kern.mode_switch::idle 0 # number of protection mode switches system.cpu08.kern.mode_good::kernel 0 system.cpu08.kern.mode_good::user 0 system.cpu08.kern.mode_good::idle 0 system.cpu08.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu08.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu08.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu08.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu08.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu08.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu08.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu08.kern.swap_context 0 # number of times the context was actually changed system.cpu09.kern.inst.arm 0 # number of arm instructions executed system.cpu09.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu09.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu09.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu09.kern.mode_switch::user 0 # number of protection mode switches system.cpu09.kern.mode_switch::idle 0 # number of protection mode switches system.cpu09.kern.mode_good::kernel 0 system.cpu09.kern.mode_good::user 0 system.cpu09.kern.mode_good::idle 0 system.cpu09.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu09.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu09.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu09.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu09.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu09.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu09.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu09.kern.swap_context 0 # number of times the context was actually changed system.cpu10.kern.inst.arm 0 # number of arm instructions executed system.cpu10.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu10.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu10.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu10.kern.mode_switch::user 0 # number of protection mode switches system.cpu10.kern.mode_switch::idle 0 # number of protection mode switches system.cpu10.kern.mode_good::kernel 0 system.cpu10.kern.mode_good::user 0 system.cpu10.kern.mode_good::idle 0 system.cpu10.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu10.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu10.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu10.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu10.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu10.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu10.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu10.kern.swap_context 0 # number of times the context was actually changed system.cpu11.kern.inst.arm 0 # number of arm instructions executed system.cpu11.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu11.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu11.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu11.kern.mode_switch::user 0 # number of protection mode switches system.cpu11.kern.mode_switch::idle 0 # number of protection mode switches system.cpu11.kern.mode_good::kernel 0 system.cpu11.kern.mode_good::user 0 system.cpu11.kern.mode_good::idle 0 system.cpu11.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu11.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu11.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu11.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu11.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu11.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu11.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu11.kern.swap_context 0 # number of times the context was actually changed system.cpu12.kern.inst.arm 0 # number of arm instructions executed system.cpu12.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu12.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu12.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu12.kern.mode_switch::user 0 # number of protection mode switches system.cpu12.kern.mode_switch::idle 0 # number of protection mode switches system.cpu12.kern.mode_good::kernel 0 system.cpu12.kern.mode_good::user 0 system.cpu12.kern.mode_good::idle 0 system.cpu12.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu12.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu12.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu12.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu12.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu12.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu12.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu12.kern.swap_context 0 # number of times the context was actually changed system.cpu13.kern.inst.arm 0 # number of arm instructions executed system.cpu13.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu13.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu13.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu13.kern.mode_switch::user 0 # number of protection mode switches system.cpu13.kern.mode_switch::idle 0 # number of protection mode switches system.cpu13.kern.mode_good::kernel 0 system.cpu13.kern.mode_good::user 0 system.cpu13.kern.mode_good::idle 0 system.cpu13.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu13.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu13.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu13.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu13.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu13.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu13.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu13.kern.swap_context 0 # number of times the context was actually changed system.cpu14.kern.inst.arm 0 # number of arm instructions executed system.cpu14.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu14.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu14.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu14.kern.mode_switch::user 0 # number of protection mode switches system.cpu14.kern.mode_switch::idle 0 # number of protection mode switches system.cpu14.kern.mode_good::kernel 0 system.cpu14.kern.mode_good::user 0 system.cpu14.kern.mode_good::idle 0 system.cpu14.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu14.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu14.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu14.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu14.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu14.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu14.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu14.kern.swap_context 0 # number of times the context was actually changed system.cpu15.kern.inst.arm 0 # number of arm instructions executed system.cpu15.kern.inst.quiesce 51 # number of quiesce instructions executed system.cpu15.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu15.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu15.kern.mode_switch::user 0 # number of protection mode switches system.cpu15.kern.mode_switch::idle 0 # number of protection mode switches system.cpu15.kern.mode_good::kernel 0 system.cpu15.kern.mode_good::user 0 system.cpu15.kern.mode_good::idle 0 system.cpu15.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches system.cpu15.kern.mode_switch_good::user nan # fraction of useful protection mode switches system.cpu15.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu15.kern.mode_switch_good::total nan # fraction of useful protection mode switches system.cpu15.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu15.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu15.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu15.kern.swap_context 0 # number of times the context was actually changed ---------- End Simulation Statistics ----------