How to build a model that is efficient for HDL conversion?

Hi, I want to build a DVB-S2 modulator model using Simulink and then implement it on an FPGA. What tips should I have in mind before starting model building?

Answer 1

[Kiran Kintali]

DVB-S2 HDL PL Header Recovery

This example shows how to implement DVB-S2 time, frequency, and phase synchronization and PL header recovery using Simulink® blocks that are optimized for HDL code generation and hardware implementation.