Modeling S-R Flip flip for HDL code generation

Sir/Madam,

For the functional model I used S-R flip flop in simulink library. I realized that the model is incompatible with HDL code generation. The HDL work flow section 2.3 flags error message: incompatible with :..Combinatorial Logic' is not supported for HDL code generation. To continue with code generation, comment out this block..."

The error is specific to the combinatorial logic block used in the S-R flip flop model available in the simulink library.

Please point me to an appropriate answer record which implements HDL compatible S-R flip flop model.

Thank You

[Bharath Venkataraman]

Do you require the S-R flip flop or will the delay block that simulates the behavior of a register meet your needs?

Answer 1

[Kiran Kintali]

Attached in an example model that works in 22a release.