HDL code generation of delay block and problem in regard to the use of verilog ce_out

조회 수: 13(최근 30일)
I'm building a PI contorller with HDL Coder, the model base rate is 80MHz, all blocks are defined with a sample rate of 16KHz.
When generating verilog with HDL Coder, it indicates a pipeline latency of 3 cycles (in case of using resource sharing for product blocks)
There are 3 important signals in the generated verilog code beside the user define input/ output ,[clk], [clk_enable] and [ce_out]
This is how I use the verilog code that it generated
  1. I give the [clk] input a 80MHz clock signal
  2. Every 62.5us(16K) send a synchronize signal which set the [clk_enable] high
  3. Then I start counting the number of [ce_out], when it counts to 4, I store the output values and set the [clk_enable] low (the first ce_out when setting clk_enable is also counted, therefore for 3 cycles latency I count to the fourth ce_out)
  4. Afterward, the model is disable untile the next synchronize signal comes in.
Problem:
  1. Am I using the model generated verilog code correctcly as it was designed?
  2. I was supposed to desgin the delay block for storing the value until the next synchronize signal come in for use in the next 62.5us cycle, however, with this method the delay block is accumulated for 3 times in one 62.5us cycle, every [ce_out] it adds the values from store from the last [ce_out].
  3. How can I make sure the delay value of this block is kept untile the next 62.5us cycle regardless the size of pipeline latency cycles?

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Kiran Kintali
Kiran Kintali 2022년 3월 4일
편집: Kiran Kintali 2022년 3월 4일
A sample model would be helpful. I built one using the info shown in the picture above.
Given there is a ratio of 5000 between clock rate and data rate the model uses Oversampling factor HDL option on the model and enables Clock Rate Pipelining was able to generate code.
>> makehdl('test_pi_ex/Subsystem')
### Generating HDL for 'test_pi_ex/Subsystem'.
### Using the config set for model test_pi_ex for HDL code generation parameters.
### Running HDL checks on the model 'test_pi_ex'.
### Begin compilation of the model 'test_pi_ex'...
### Applying HDL optimizations on the model 'test_pi_ex'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Output port 2: 1 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'test_pi_ex'.
### MESSAGE: The design requires 5000 times faster clock with respect to the base rate = 1.
### Working on test_pi_ex/Subsystem/nfp_relop_single as hdlsrc\test_pi_ex\nfp_relop_single.vhd.
### Working on test_pi_ex/Subsystem/nfp_relop_single as hdlsrc\test_pi_ex\nfp_relop_single_block.vhd.
### Working on test_pi_ex/Subsystem/nfp_add_single as hdlsrc\test_pi_ex\nfp_add_single.vhd.
### Working on test_pi_ex/Subsystem/nfp_mul_single as hdlsrc\test_pi_ex\nfp_mul_single.vhd.
### Working on test_pi_ex/Subsystem/nfp_sub_single as hdlsrc\test_pi_ex\nfp_sub_single.vhd.
### Working on Subsystem_tc as hdlsrc\test_pi_ex\Subsystem_tc.vhd.
### Working on test_pi_ex/Subsystem as hdlsrc\test_pi_ex\Subsystem.vhd.
### Generating package file hdlsrc\test_pi_ex\Subsystem_pkg.vhd.
### Code Generation for 'test_pi_ex' completed.
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'test_pi_ex' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
>>
Add a valid testbench source blocks to the attached model and generate HDL testbench using HDL Coder and observe the results.
>> hdlsaveparams('test_pi_ex')
%% Set Model 'test_pi_ex' HDL parameters
hdlset_param('test_pi_ex', 'FloatingPointTargetConfiguration', hdlcoder.createFloatingPointTargetConfig('NativeFloatingPoint'));
hdlset_param('test_pi_ex', 'HDLSubsystem', 'test_pi_ex');
hdlset_param('test_pi_ex', 'Oversampling', 5000);
% Set SubSystem HDL parameters
hdlset_param('test_pi_ex/Subsystem', 'SharingFactor', 2);
Setting SharingFactor to share the two Multipliers in the model should also work.
>> makehdl('test_pi_ex/Subsystem')
### Generating HDL for 'test_pi_ex/Subsystem'.
### Using the config set for model test_pi_ex for HDL code generation parameters.
### Running HDL checks on the model 'test_pi_ex'.
### Begin compilation of the model 'test_pi_ex'...
### Applying HDL optimizations on the model 'test_pi_ex'...
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Output port 2: 1 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'test_pi_ex'.
### MESSAGE: The design requires 5000 times faster clock with respect to the base rate = 1.
### Working on nfp_mul_single as hdlsrc\test_pi_ex\nfp_mul_single.vhd.
### Working on crp_temp_shared as hdlsrc\test_pi_ex\crp_temp_shared.vhd.
### Working on test_pi_ex/Subsystem/nfp_relop_single as hdlsrc\test_pi_ex\nfp_relop_single.vhd.
### Working on test_pi_ex/Subsystem/nfp_relop_single as hdlsrc\test_pi_ex\nfp_relop_single_block.vhd.
### Working on test_pi_ex/Subsystem/nfp_add_single as hdlsrc\test_pi_ex\nfp_add_single.vhd.
### Working on test_pi_ex/Subsystem/nfp_sub_single as hdlsrc\test_pi_ex\nfp_sub_single.vhd.
### Working on Subsystem_tc as hdlsrc\test_pi_ex\Subsystem_tc.vhd.
### Working on test_pi_ex/Subsystem as hdlsrc\test_pi_ex\Subsystem.vhd.
### Generating package file hdlsrc\test_pi_ex\Subsystem_pkg.vhd.
### Code Generation for 'test_pi_ex' completed.
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'test_pi_ex' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
>>
If you have additional questions on the generated code please feel free to reach out to support team at MathWorks.
  댓글 수: 4
Steven Zeng
Steven Zeng 2022년 4월 11일
Kiran, how can I identify the minimum Oversampling factor that I can use? If I change the oversampling factor to 40 instead of 5000, how can I fit the generated code into the design with 16KHz data rate and 80MHz clock rate.

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