AXI4-Stream IIO Read

Read AXI4-Stream Data using IIO

  • Library:
  • Embedded Coder Support Package for Xilinx Zynq Platform

Description

This block reads data from the direct-memory-access (DMA) buffer of the specified AXI4-Stream IP core device by using the Industrial I/O (IIO) library drivers. The AXI4-Stream IIO Read block enables you to achieve a low-latency, high-throughput data transmission between your model deployed on the processor and the IP core on the FPGA. This diagram shows the control signals and path of the data before it reaches this block..

Ports

Output

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This port outputs the N-by-1 vector received from the DMA buffer transfer. Use the Frame size parameter to determine the number of samples read for each DMA transfer. This port is unnamed until the Valid port is enabled.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

This port outputs a validation flag indicating a successful read of the data from the IP core, where 1 indicates a successful read.

Dependencies

To enable this port, set Data timeout (seconds) to a finite value.

Data Types: Boolean

Parameters

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Enter the name and channel of the IP core on the FPGA as a colon separated list. If you are using HDL Coder™ to generate the IP core, HDL Coder maps the IP core to mwipcore0 and uses channel s2mm0. For more information on getting IIO device names and channels, see Tips.

Enter the size of the data vector to be read from the IP core device.

Select the data type used by the IP core.

The signal data output by the AXI4-Stream IIO Read blocks polls from the DMA buffer using the AXI4-Stream protocol. The Sample time or base-rate of the subsystem specifies the polling rate of the DMA buffer.

Specify the maximum time out delay for the DMA stream read.

Tips

  • To get a list of available IIO device names and channels, open a terminal into the Xilinx® Zynq® hardware board, and execute this command.

    iio_info

Introduced in R2018b