Write data to IP core on Xilinx Zynq Platform
This block writes a data vector to a contiguous group of memory-mapped registers on an HDL Coder™ generated IP core. The AXI4-Interface Write block, using the central interconnect of the processing system, provides simple memory-mapped communication with the IP core on the FPGA. This block is best suited for low-throughput communication, such as setting status, state, or control registers. This diagram shows the path of the data after it leaves this block.
Port_1 — Input signal to IP core registers
Specify the N-by-1 vector written to memory-mapped registers on the IP core, starting at Register offset.
Device name — Path and name of IP core device
/dev/mwipcore (default) | character array
Enter the path and name of the IP core.
If you use HDL Coder to generate the IP core, HDL Coder maps the IP core to
Register offset — Offset of register from base address of IP core
hex2dec( '010C' ) (default) | decimal number character array
Enter the offset of the register from the base address of the IP core. The
block writes data to this register. When you use a hexadecimal number
character vector to specify the address offset, represent the value as an
argument inside the
If you use HDL Coder to generate the IP core, you can get the value of the address offset from the “Register Address Mapping” section of the Custom IP Core Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).
Introduced in R2013a
AXI4-Interface Read | AXI4-Stream IIO Read | AXI4-Stream IIO Write
- Model Design for AXI4-Stream Interface Generation (HDL Coder Support Package for Xilinx Zynq Platform)