This example shows you how to communicate with the FPGA IP core on the Zynq hardware using AXI4®-Lite protocol. AXI4 (Advanced eXtensible Interface 4) is an ARM® standard.
Xilinx Zynq family processors consists of a dual-core ARM Cortex-A9® with an Artix®-7 or Kintex®-7 FPGA. On these devices, the processor is connected to the FPGA via AXI4 interface.
In this example you will learn how to build a Simulink model and run ARM executable on Zynq hardware that communicates with the FPGA IP core using AXI4-Lite protocol. This example is the final step of integration in the hardware-software co-design workflow for Xilinx Zynq Platform. Click here to get more information about this workflow.
We recommend completing Getting started with Xilinx Zynq hardware example if you followed the setup steps and configured the Zynq hardware to run Linux operating system.
We recommend completing Getting Started with VxWorks® 7 on Xilinx Zynq Platform if you followed the setup steps and configured the Zynq hardware to run VxWorks® 7 operating system.
This example requires the following board:
Xilinx Zynq ZC702 evaluation kit
Note: Set up the Xilinx Zynq ZC702 evaluation kit as shown in the figure below. To learn more about the ZC702 hardware setup, please refer to Xilinx documentation.
In this task you will configure the Simulink model to send and receive data from the FPGA IP core. Following figure shows the architecture of the FPGA IP core that is connected to the processor through AXI4-Lite interface. ARM executable controls the AXI4-Lite accessible (memory-mapped) registers and tunes the parameters of the algorithm in the IP core.
The following figure shows the simulation model.
1. Open the FPGA IP core simulation model. The led_counter subsystem represents the logic of the FPGA IP core. The FPGA IP core and bitstream were pre-generated for convenience.
To customize this design and to generate your FPGA IP core using HDL Coder® follow the Getting Started with Hardware-Software Codesign Workflow for Xilinx Zynq Platform.
2. Simulate the model and observe the counter waveforms. The Read_back output of the led_counter subsystem counts up from 1 through 255 in the steps of .
Following figure shows the model from which you will generate ARM executable. In this task, you will configure the model to generate ARM executable and run it on the Zynq hardware.
1. Open the AXI4-Lite software interface model.
2. Double-click on the
3. In the Simulink model, click View > Library Browser.
4. In the Simulink Library Browser, navigate to Embedded Coder Support Package for Xilinx Zynq Platform.
5. Follow the instructions given in the yellow annotation blocks of
Note: The FPGA IP core registers mapping for the
led_counter subsystem is shown in the following figure. The offset address values are derived from this table.
For convenience, a pre-configured model is provided.
This model is configured for generating code on Zynq hardware running Linux operating system. To configure it for VxWorks 7, follow Getting Started with VxWorks® 7 on Xilinx Zynq Platform.
In this task, you will run the Simulink model in external mode and control the FPGA IP core on Zynq hardware. This task requires Zynq hardware to be connected and powered on. The executable running on the ZC702 hardware will blink the LEDs connected to the FPGA. The LED positions on ZC702 hardware are shown in the figure below:
1. Double-click the Program FPGA subsystem block, to automatically download the pre-generated bitstream.
2. In the model, click Simulation > Run to start the external mode simulation.
Wait for the model build and executable download to complete. Once the external mode simulation starts you will see the waveforms on the Scope. Double-click the Slider gain block to control the speed of the counter. Double-click the Manual Switch block to control the direction of the counter.
3. Stop external mode simulation by clicking Simulation > Stop in the model.
This example showed the steps to configure a Simulink model and use the AXI4-Lite blocks to communicate with FPGA IP core AXI4-Lite protocol.