Default System Reference Design

The HDL Coder™ software can generate an IP core with an AXI4 or an AXI4-Lite interface. You can integrate the HDL IP core into the Default system reference design.

The Default system is a basic reference design that contains an ARM processor and the HDL IP core. HDL Coder generates the HDL DUT IP core, and inserts it into the reference design. The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite interface, the processor can read and write data to and from the IP core. You can tune the parameters on the FPGA, or probe the results from the FPGA via the AXI4-Lite interface in the IP core. To tune the parameters or probe results, use this reference design with External mode in Simulink^®.

To specify the Default system as the target reference design:

1. Specify IP Core Generation as target workflow. Open the HDL Workflow Advisor. In the Set Target Device and Synthesis Tool task, specify IP Core Generation as the Target workflow.

   

2. Specify Default system as target reference design. In the Set Target Reference Design task, for Reference design, select Default system. You can also specify whether you want the code generator to automatically insert the JTAG MATLAB AXI Master IP in the reference design. For an example, see Using JTAG MATLAB as AXI Master to control the HDL Coder IP Core.

   

Go through the workflow to generate the HDL IP core, and integrate the IP core into the Default system reference design.

Related Topics

• Getting Started with Targeting Xilinx Zynq Platform
• Getting Started with Targeting Intel SoC Devices