Documentation

Modeling

Model your algorithm in Simulink® by using a simplified protocol for mapping to AXI4-Stream, AXI4-Stream Video, or AXI4 Master interfaces

With the HDL Coder™ software, you can implement a simplified protocol in your model for AXI4-Stream, AXI4-Stream Video, or AXI4 Master mapping. The software generates an HDL IP core with the corresponding interfaces.

Topics

Model Design for AXI4 Slave Interface Generation (HDL Coder)

How to design your model for AXI4 or AXI4-Lite interfaces for scalar or vector ports and read back values.

Model Design for AXI4-Stream Interface Generation

How to design your model for AXI4-Stream vector or scalar interface generation

Model Design for AXI4-Stream Video Interface Generation

How to design your model for IP core generation with AXI4-stream video interfaces

Model Design for AXI4 Master Interface Generation (HDL Coder)

Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.

Featured Examples