Xilinx FPGA Board Support from HDL Verifier

HDL Verifier™ automates the verification of HDL code on FPGA boards by providing connections between your FPGA board and your simulations in Simulink® or MATLAB®.

  • FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an FPGA board.

  • FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.

  • MATLAB AXI master provides access to live on-board memory locations from MATLAB. You must include the MATLAB AXI master IP in your FPGA design.

To use each of these features, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.

Supported Xilinx FPGA Boards

This support package enables FPGA-in-the-loop simulation for the boards in the table. FPGA data capture and MATLAB AXI master are supported for Xilinx® 7-series FPGAs, Xilinx Zynq®-7000, or newer devices using Vivado® projects. Xilinx ISE projects are not supported. Your Xilinx FPGA board must use a Digilent® USB-to-JTAG cable.

Device FamilyBoardEthernet (FIL)JTAG (FIL, AXI Master, Data Capture)PCI Express (FIL)[a]Comments

Xilinx Artix®-7

Digilent Nexys™4 Artix-7

xx  
Digilent Arty Board x  

Xilinx Kintex®-7

Kintex-7 KC705xxx 

Xilinx Kintex UltraScale™

Kintex UltraScale FPGA KCU105 Evaluation Kit

xx  

Xilinx Kintex UltraScale+™

Kintex UltraScale+ FPGA KCU116 Evaluation Kit

 x For more information, see PCI Express MATLAB as AXI Master.

Xilinx Spartan®-6

Spartan-6 SP605x   
Spartan-6 SP601x   
XUP Atlys Spartan-6x   

Xilinx Spartan-7

Digilent Arty S7-25xx  

Xilinx Virtex® UltraScale

Virtex UltraScale FPGA VCU108 Evaluation Kit

xx  

Xilinx Virtex UltraScale+

Virtex UltraScale+ FPGA VCU118 Evaluation Kit

 xx 

Xilinx Virtex-7

Virtex-7 VC707xxx 
Virtex-7 VC709 xx 

Xilinx Virtex-6

Virtex-6 ML605x   

Xilinx Virtex-5

Virtex ML505x   
Virtex ML506x   
Virtex ML507x   
Virtex XUPV5–LX110Tx   

XilinxVirtex-4

Virtex ML401x  

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex ML402x  
Virtex ML403x  

Xilinx Zynq

Zynq-7000 ZC702

 x  
Zynq-7000 ZC706  x  
ZedBoard™  x Use the USB port marked "PROG" for programming.

ZYBO™ Zynq-7000 Development Board

 x  
PicoZed™ SDR Development Kit x  
MiniZed™  x Supported only for Data Capture and AXI-Master via FTDI JTAG.

Xilinx Zynq UltraScale+

Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

 x  

Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

[a] FIL over PCI Express® connection is supported only for 64-bit Windows® operating systems.

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