Specify the expected C28x CPU clock frequency and match the same in your C28x Model. The C28x CLOCK is the same as PLLSYSCLK. The M3 Clock is a factor of M3SSDIVSEL divided by the PLLSYSCLK.
Specify the frequency of the crystal oscillator used in the board. In case of Concerto the crystal oscillator is external to the processor.
The option that helps you to set the PLL control register value automatically. When you select this check box, the values in the SYSPLLMULT, SYSDIVSEL , and the Achievable C28x SYSCLK in MHz parameters are automatically calculated based on the Desired C28x CPU Clock value entered on the Board.
Specify the system PLL multiplier. You can specify a value in this parameter if Auto set PLL based on OSCCLK and CPU clock is not selected. The PLL multiplier is a 9 bit field with 7 bits of the SYSPLLMULT register comprising of the integer portion and the remaining 2 bits for the fractional portion. You can enter a value in the range between 0 to 127.75 with multiples of 0.25 for fractional portion of the value.
If you select the Auto set PLL based on OSCCLK and CPU clock check box, the auto calculated clock divider value achieves the specified CPU Clock value based on the Oscillator clock frequency. Otherwise, you can select a value for Clock divider (SYSDIVSEL).
The auto calculated feedback value that matches most closely to the desired CPU Clock value on the board, based on the values of OSCCLK, SYSPLLMULT, and the SYSDIVSEL.
Select a value from the options for M3 system clock divider. The C28 CLKIN clock is divided by the selected value to generate the M3 CPU clock.
This is the achievable M3 system clock frequency. This is calculated based on the values of OSCCLK, SYSPLLMULT, SYSDIVSEL, and M3SSDIVSEL.