C28x-I2C

You can set the following parameters for I2C:

Mode

Configure the I2C module as Master or Slave.

If a module is an I2C master, it:

  • Initiates communication with slave nodes by sending the slave address and requesting data transfer to or from the slave.

  • Outputs the Master clock frequency on the serial clock line (SCL) line.

If a module is an I2C slave, it:

  • Synchronizes itself with the serial clock line (SCL) line.

  • Responds to communication requests from the master.

In Slave mode, you can configure the Addressing format, Address register, and Bit count parameters.

The Mode parameter corresponds to bit 10 (MST) of the I2C mode register (I2CMDR).

Addressing format

In Slave mode, determines the addressing format of the I2C master and sets the I2C module to the same mode:

  • 7-Bit Addressing—the normal address mode.

  • 10-Bit Addressing—the expanded address mode.

  • Free Data Format—a mode that does not use addresses. (If you Enable loopback, the Free data format is not supported.)

The Addressing format parameter corresponds to bit 3 (FDF) and bit 8 (XA) of the I2C mode register (I2CMDR).

Own address register

In Slave mode, enter the 7-bit (0–127) or 10-bit (0–1023) address that the I2C module uses while it is a slave.

This parameter corresponds to bits 9–0 (OAR) of the I2C own address register (I2COAR).

Bit count

In Slave mode, sets the number of bits in each data byte the I2C module transmits and receives. This value must match that of the I2C master.

This parameter corresponds to bits 2–0 (BC) of the I2C mode register (I2CMDR).

Module clock prescaler (IPSC: 0 to 255)

In Master mode, configures the module clock frequency by entering a value 0–255, inclusive.

Module clock frequency = I2C input clock frequency / (Module clock prescaler + 1)

The I2C specifications require a module clock frequency between 7 MHz and 12 MHz.

The I2C input clock frequency depends on the DSP input clock frequency and the value of the PLL control register divider (PLLCR). For more information on setting the PLLCR, see the documentation for your digital signal controller.

The Module clock prescaler (IPSC: 0 to 255) corresponds to bits 7–0 (IPSC) of the I2C prescaler register (I2CPSC).

I2C Module clock frequency (SYSCLKOUT / (IPSC+1)) in Hz

Display the frequency the I2C module uses internally. To set this value, change the Module clock prescaler.

For more information about this value, see the “Formula for the Master Clock Period” section in the TMS320x280x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721, on the Texas Instruments™ website.

I2C Master clock frequency (Module Clock Freq/(ICCL+ICCH+10)) in Hz

Display the master clock frequency.

For more information about this value, see the “Clock Generation” section in the TMS320x280x/ TMS320F28M35x/ TMS320F28M36x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721/ SPRUH22F/ SPRUHE8B, available on the Texas Instruments website.

Master clock Low-time divider (ICCL: 1 to 65535)

In Master mode, the divider determines the duration of the low state of the serial clock line (SCL) on the I2C bus.

The low-time duration of the master clock = Tmod x (ICCL + d).

For more information, see the “Formula for the Master Clock Period” section in the TMS320x280x/ TMS320F28M35x/ TMS320F28M36x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A/ SPRUH22F/ SPRUHE8B, available on the Texas Instruments website.

This parameter corresponds to bits 15–0 (ICCL) of the clock low-time divider register (I2CCLKL).

Master clock High-time divider (ICCH: 1 to 65535)

In Master mode, the divider determines the duration of the high state of the serial clock line (SCL) on the I2C bus.

The high-time duration of the master clock = Tmod x (ICCL + d).

For more information about this value, see the “Formula for the Master Clock Period” section in the TMS320x280x/ TMS320F28M35x/ TMS320F28M36x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A, SPRUH22f, SPRUHE8B, available on the Texas Instruments website.

This parameter corresponds to bits 15–0 (ICCH) of the clock high-time divider register (I2CCLKH).

Enable loopback

In Master mode, enables or disables digital loopback mode. In digital loopback mode, I2CDXR transmits data over an internal path to I2CDRR, which receives the data after a configurable delay.

The delay, measured in DSP cycles, equals (I2C input clock frequency/module clock frequency) x 8.

While Enable loopback is enabled, free data format addressing is not supported.

This parameter corresponds to bit 6 (DLB) of the I2C mode register (I2CMDR).

SDA pin assignment

Select a GPIO pin as I2C data bidirectional port.

This parameter is not available for TI C2000™ F280x, F28044, F2833x, and C2834x processors.

SCL pin assignment

Select a GPIO pin as I2C clock bidirectional port.

This parameter is not available for TI C2000 F280x, F28044, F2833x, and C2834x processors.

Enable Tx interrupt

This parameter corresponds to bit 5 (TXFFIENA) of the I2C transmit FIFO register (I2CFFTX).

Tx FIFO interrupt level

This parameter corresponds to bits 4–0 (TXFFIL4-0) of the I2C transmit FIFO register (I2CFFTX).

Enable Rx interrupt

This parameter corresponds to bit 5 (RXFFIENA) of the I2C receive FIFO register (I2CFFRX).

Rx FIFO interrupt level

This parameter corresponds to bit 4–0 (RXFFIL4-0) of the I2C receive FIFO register (I2CFFRX).

Enable system interrupt

Select this parameter to configure the five basic I2C interrupt request parameters in the interrupt enable register (I2CIER):

  • Enable AAS interrupt

  • Enable SCD interrupt

  • Enable ARDY interrupt

  • Enable NACK interrupt

  • Enable AL interrupt

Enable AAS interrupt

Enable the addressed-as-slave interrupt.

When enabled, the I2C module generates an interrupt (AAS bit = 1) upon receiving one of the following:

  • Its Own address register value

  • A general call (all zeros)

  • A data byte in free data format

When enabled, the I2C module clears the interrupt (AAS = 0) upon receiving one of the following:

  • Multiple START conditions (7-bit addressing mode only)

  • A slave address that is different from Own address register (10-bit addressing mode only)

  • A NACK or a STOP condition

This parameter corresponds to bit 6 (AAS) of the interrupt enable register (I2CIER).

Enable SCD interrupt

Enable STOP condition detected interrupt.

When enabled, the I2C module generates an interrupt (SCD bit = 1) after the CPU detects a stop condition on the I2C bus.

When enabled, the I2C module clears the interrupt (SCD = 0) upon one of the following events:

  • The CPU reads I2CISRC while it indicates a stop condition

  • A reset of the I2C module

  • Someone manually clears the interrupt

This parameter corresponds to bit 5 (SCD) of the interrupt enable register (I2CIER).

Enable ARDY interrupt

Enable register-access-ready interrupt enable bit.

When enabled, the I2C module generates an interrupt (ARDY bit = 1) after the previous address, data, and command values in the I2C module registers have been used. New values can be written to the I2C module registers.

This parameter corresponds to bit 2 (ARDY) of the interrupt enable register (I2CIER).

Enable NACK interrupt

Enable no acknowledgment interrupt enable bit.

When enabled, the I2C module generates an interrupt (NACK bit = 1) when the module operates as a transmitter in master or slave mode and receives a NACK condition.

This parameter corresponds to bit 1 (NACK) of the interrupt enable register (I2CIER).

Enable AL interrupt

Enable arbitration-lost interrupt.

When enabled, the I2C module generates an interrupt (AL bit = 1) when the I2C module operates as a master transmitter and looses an arbitration contest with another master transmitter.

This parameter corresponds to bit 0 (AL) of the interrupt enable register (I2CIER).

For more information about the I2C parameters, see the TMS320x280x/ TMS320F28M35x/ TMS320F28M36x Inter-Integrated Circuit Module Reference Guide, Literature Number: SPRU721A/ SPRUH22F/ SPRUHE8B available on the Texas Instruments website.

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