C28x-EMIF

Use the external memory interface (EMIF) to connect the C2000™ processor to an external synchronous or asynchronous memory.

For C2000 processors, the EMIF is supported for these memory devices:

  • Synchronous memory interface — JESD21-C SDR SDRAM

  • Asynchronous memory interface — SRAM, NOR Flash, or any external device

Based on the processors, the number of EMIF modules supported varies. When you configure the EMIF interface based on the memory used, the GPIO pins required for interacting with the memory through EMIF are also configured. You must ensure that these GPIO pins are not used with other peripherals or as input/output because these pins are not included in the existing conflict check.

The EMIF1 pin configuration for synchronous and asynchronous memory is:

  • GPIO38 – GPIO52 (except GPIO42 and GPIO43) are configured as address pins A0 – A12.

  • GPIO86 and GPIO87 are configured as address pins A13 and A14 only when asynchronous memory is selected. GPIO86 and GPIO87 are configured as row and column address select (RAS and CAS) when synchronous memory is selected.

  • GPIO69 – GPIO85 are configured as data pins D15 – D0. GPIO53 – GPIO68 are configured as data pins D31 – D16 only for 32-bit memory configuration.

  • GPIO88 – GPIO91 are configured as data mask pins DQM0 – DQM3. You can manually configure these pins using custom code as address pins A15 – A18 when the EMIF is configured only for 8-bit asynchronous memory.

  • GPIO92 and GPIO93 are configured as banks BA1 and BA0.

  • GPIO28 – GPIO37 are configured as chip select (CS2, CS3, and CS4), clock enable (SDCKE), clock (CLK), write enable (WE), read and write control (RNW), wait pin (WAIT), and enable pin (OE).

The EMIF2 pin configuration for synchronous and asynchronous memory is:

  • GPIO98 – GPIO109 are configured as address pins A0 – A11.

  • GPIO53 – GPIO68 are configured as data pins D15 – D0.

    An error message is displayed if the EMIF2 CS# is selected when the EMIF1 is configured for 32-bit data width because the same GPIO pins are used as D31 – D16 for the EMIF1 in 32-bit configuration.

  • GPIO96 – GPIO97 are configured as data mask pins DQM0 – DQM1.

  • GPIO111 and GPIO112 are configured as banks BA1 and BA0.

  • GPIO110 and GPIO113 – GPIO121 are configured as chip select (CS0 and CS2), row and column address select (RAS and CAS), clock enable (SDCKE), clock (CLK), write enable (WE), read and write control (RNW), wait pin (WAIT), and enable pin (OE).

You can set these parameters for the EMIF:

EMIF clock divider (EMIF#CLKDIV)

Select the clock divider for the EMIF# module clock generation. In this case, # represents the number of the EMIF module. The EMIF clock frequency is based on SYSCLKOUT.

Enable CS0 for Synchronous memory

Select the chip select (CS0) to interface with the synchronous dynamic RAM (SDRAM). Synchronous memory supports the following memory sizes and addresses:

  • EMIF1_CS0 — Data memory of size 256M × 16 with an address range of 0x80000000 to 0x8FFFFFFF

  • EMIF2_CS0 — Data memory of size 3M × 16 with an address range of 0x90000000 to 0x91FFFFFF

Creation and usage of variables in SDRAM require the use of volatile qualifier and far attribute. Use #pragma to place the variables in SDRAM memory sections. Custom storage classes EM1_CS0_MEMORY and EM2_CS0_MEMORY are created in the signal object class tic2000demospkg.Signal to handle these requirements. You can use these custom storage classes to create variables using the Data Store Memory blocks.

Enable CS# for Asynchronous memory

Select the chip select (CS2/CS3/CS4) to interface with the asynchronous memory (SRAM / NOR Flash). Asynchronous memory supports the following memory sizes and addresses:

  • EMIF1_CS2 — Data memory of size 2M × 16 with an address range of 0x00100000 to 0x002FFFFF

  • EMIF1_CS3 — Data memory of size 512k × 16 with an address range of 0x00300000 to 0x0037FFFF

  • EMIF1_CS4 — Data memory of size 393k × 16 with an address range of 0x00380000 to 0x003DFFFF

  • EMIF2_CS2 — Data memory of size 4k × 16 with an address range of 0x00002000 to 0x00002FFF

Use #pragma to place the variables in asynchronous memory sections. Custom storage classes EM1_CS2_MEMORY, EM1_CS3_MEMORY, EM1_CS4_MEMORY, and EM2_CS2_MEMORY are created in the signal object class tic2000demospkg.Signal to handle these requirements. You can use these custom storage classes to create variables using the Data Store Memory blocks.

SDRAM column address bits

Select the value of the column address bits, thereby selecting the required page size of the connected SDRAM. Column address bits 8, 9, 10, and 11 corresponding to 256, 512, 1024, and 2048-word pages are supported.

The parameter Page size = (2^column address bits) is calculated based on the SDRAM column address bits parameter value.

Number of internal SDRAM banks

Select the number of memory banks inside the connected SDRAM. SDRAM with 1, 2, and 4 banks are supported.

SDRAM data bus width in bits

Select the data bus width of the connected SDRAM. Data bus widths of 16- and 32-bit are supported.

Refresh to active command delay cycles (T_RFC)

The minimum number of EM#CLK cycles from the refresh or load mode command to the refresh or activate command in the connected SDRAM. In this case, # represents 1 or 2. Some devices refer to this parameter as minimum auto refresh period.

The parameter t_rfc in ns = (T_RFC+1)/fEM#CLK is calculated based on the Refresh to active command delay cycles (T_RFC) parameter value.

Row precharge to active command delay cycles (T_RP)

The minimum number of EM#CLK cycles required from the row precharge command to the activate or refresh command in the connected SDRAM.

The parameter t_rp in ns = (T_RP+1)/fEM#CLK is calculated based on the Row precharge to active command delay cycles (T_RP) parameter value.

Active to read or write command delay cycles (T_RCD)

The minimum number of EM#CLK cycles from the activate command to the read or write command in the connected SDRAM.

The parameter t_rcd in ns = (T_RCD+1)/fEM#CLK is calculated based on the Active to read or write command delay cycles (T_RCD) parameter value.

Last write to row precharge command delay cycles (T_WR)

The minimum number of EM#CLK cycles from the last write transfer or last data in command to the row precharge command in the connected SDRAM.

The parameter t_wr in ns = (T_WR+1)/fEM#CLK is calculated based on the Last write to row precharge command delay cycles (T_WR) parameter value.

Active to precharge command delay cycles (T_RAS)

The minimum number of EM#CLK cycles from the activate command to the row precharge command in the connected SDRAM.

The parameter t_ras in ns = (T_RAS+1)/fEM#CLK is calculated based on the Active to precharge command delay cycles (T_RAS) parameter value.

Active to active command delay cycles (T_RC)

The minimum number of EM#CLK cycles from an activate command to the next activate command in the same bank in the connected SDRAM. This is also known as the minimum auto refresh period.

The parameter t_rc in ns = (T_RC+1)/fEM#CLK is calculated based on the Active to active command delay cycles (T_RC) parameter value.

Active one bank to active another bank command delay cycles (T_RRD)

The minimum number of EM#CLK cycles from an activate command in one bank to an activate command in a different bank in the connected SDRAM.

The parameter t_rrd in ns = (T_RRD+1)/fEM#CLK is calculated based on the Active one bank to active another bank command delay cycles (T_RRD) parameter value.

Self-refresh exit to other command delay cycles (T_XSR)

The minimum number of EM#CLK cycles from the self refresh exit command to any other command in the connected SDRAM.

The parameter t_xsr in ns = (T_XSR+1)/fEM#CLK is calculated based on the Self-refresh exit to other command delay cycles (T_XSR) parameter value.

SDRAM refresh period (tRefreshPeriod) in ms

REFRESH_RATE for SDRAM defines the rate at which the connected SDRAM refreshes. SDRAM refresh rate depends on the values of SDRAM refresh period (tRefreshPeriod) in ms and SDRAM refresh cycle (ncycles). Enter the SDRAM refresh period and SDRAM refresh cycles from the SDRAM datasheet. The SDRAM refresh rate is calculated based on the formula tRefreshPeriod * EMIF clock frequency / ncycles.

SDRAM CAS Latency

Select the CAS latency required to access the connected SDRAM. SDRAM devices with CAS latencies of 2 and 3 are supported.

Asynchronous mode

Select the asynchronous mode for the connected asynchronous memory. These are the available modes:

  • Normal — The byte enable will be active during the entire asynchronous cycle.

  • Strobe — The byte enable will be active only during the strobe period of the access cycle mode.

Asynchronous data bus width in bits

Select the data bus width of the connected asynchronous memory. Asynchronous memory data bus width of 8-, 16-, and 32-bit are supported.

Read strobe setup cycles (R_SETUP)

The number of EM#CLK cycles from the EMIF chip select to the pin enable for asynchronous memory assert.

The parameter t_r_setup in ns = (R_SETUP+1)/fEM#CLK is calculated based on the Read strobe setup cycles (R_SETUP) parameter value.

Read strobe duration cycles (R_STROBE)

The number of EM#CLK cycles during which the pin enable for the asynchronous memory is held active.

The parameter t_r_strobe in ns = (R_STROBE+1)/fEM#CLK is calculated based on the Read strobe duration cycles (R_STROBE) parameter value.

Read strobe hold cycles (R_HOLD)

The number of EM#CLK cycles during which the EMIF chip select is held active after pin enable for the asynchronous memory is deasserted.

The parameter t_r_hold in ns = (R_HOLD+1)/fEM#CLK is calculated based on the Read strobe hold cycles (R_HOLD) parameter value.

Write strobe setup cycles (W_SETUP)

The number of EM#CLK cycles from the EMIF chip select to the write enable for the asynchronous memory assert.

The parameter t_w_setup in ns = (W_SETUP+1)/fEM#CLK is calculated based on the Read strobe hold cycles (R_HOLD) parameter value.

Write strobe duration cycles (W_STROBE)

The number of EM#CLK cycles during which the write enable for the asynchronous memory is held active.

The parameter t_w_strobe in ns = (W_STROBE+1)/fEM#CLK is calculated based on the Write strobe duration cycles (W_STROBE) parameter value.

Write strobe hold cycles (W_HOLD)

The number of EM#CLK cycles during which the EMIF chip select is held active after write enable for the asynchronous memory is deasserted.

The parameter t_w_hold in ns = (W_HOLD+1)/fEM#CLK is calculated based on the Write strobe hold cycles (W_HOLD) parameter value.

Turn around cycles (TA)

The number of EM#CLK cycles between the end of one asynchronous memory access and the start of another asynchronous memory access. This delay is not incurred between a read followed by a read or a write followed by a write to the same chip select.

Enable extended wait mode

Select this option to enable the extended wait option for the asynchronous memory. This option can be used if extended asynchronous wait cycles are required based on the EM#WAIT pin.

Maximum extended wait cycles for Asynchronous memory (MAX_EXT_WAIT) [0–255]

This option is enabled if extended wait for any of the asynchronous memory CS# is enabled. Based on the value entered, the EMIF waits for (MAX_EXT_WAIT+1) * 16 clock cycles before the asynchronous cycle is terminated.

Pin polarity of extended wait

Select the option to make the EMIF wait if the pin is low or high. This option is enabled when the extended wait mode of any of the asynchronous memory CS2/CS3/CS4 is enabled.

Enable wait rise interrupt

Select this option to get an interrupt based on the detection of a rising edge on the EM#WAIT pin. This option is enabled when the extended wait mode of any of the asynchronous memory CS2/CS3/CS4 is enabled.

Enable timeout interrupt

Select this option to get an interrupt when the EM#WAIT pin does not become inactive within the number of cycles defined in Maximum extended wait cycles for Asynchronous memory (MAX_EXT_WAIT) [0–255]. This option is enabled when the extended wait mode of any of the asynchronous memory CS2/CS3/CS4 is enabled.

Enable line trap interrupt

Select this option to get an interrupt when there is an invalid cache line size or illegal memory access.

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