C281x PWM

Pulse width modulators (PWMs)

Library

Embedded Coder® Support Package for Texas Instruments™ C2000™ Processors/ C281x

Description

F2812 DSPs include a suite of pulse width modulators (PWMs) used to generate various signals. This block provides options to set the A or B module Event Managers to generate the waveforms you require. The twelve PWMs are configured in six pairs, with three pairs in each module.

The C281x PWM module shares GP Timers with other C281 blocks. For more information and guidance on sharing timers, see Sharing General Purpose Timers Between C281x Peripherals.

Note

All inputs to the C281x PWM block must be scalar values.

Parameters

Timer Pane

Module

Specify which target PWM pairs to use:

  • A — Displays the PWMs in module A (PWM1/PWM2, PWM3/PWM4, and PWM5/PWM6).

  • B — Displays the PWMs in module B (PWM7/PWM8, PWM9/PWM10, and PWM11/PWM12).

    Note

    PWMs in module A use Event Manager A, Timer 1, and PWMs in module B use Event Manager B, Timer 3.

Waveform period source

Source from which the waveform period value is obtained. Select Specify via dialog to enter the value in Waveform period or select Input port to use a value from the input port.

Note

All inputs to the C281x PWM block must be scalar values.

Waveform period

Period of the PWM waveform measured in clock cycles or in seconds, as specified in the Waveform period units.

Note

The term clock cycles refers to the high-speed peripheral clock on the F2812 chip. This clock is 75 MHz by default because the high-speed peripheral clock prescaler is set to 2 (150 MHz/2).

Waveform type (counting mode)

Type of waveform to be generated by the PWM pair. The F2812 PWMs can generate two types of waveforms: Asymmetric(Up) and Symmetric(Up-down). The following illustration shows the difference between the two types of waveforms.

Waveform period units

Units in which to measure the waveform period. Options are Clock cycles, which refer to the high-speed peripheral clock on the F2812 chip (75 MHz), or Seconds. Changing these units changes the Waveform period value and the Duty cycle value and Duty cycle units selection.

Timer prescaler

Divide the clock input to produce the desired timer counting rate.

Outputs Pane

Enable PWM#/PWM#

Check to activate the PWM pair. PWM1/PWM2 are activated via the Output 1 pane, PWM3/PWM4 are on Output 2, and PWM5/PWM6 are on Output 3.

Duty cycle source

Select Specify via dialog to use the dialog box to enter a Duty cycle value for the pair of PWM outputs. Select Input port to use the input port, W#, to enter a Duty cycle value for the pair of PWM outputs.

The input port W1 corresponds to PWM1/PWM2. W2 corresponds to PWM3/PWM4. W3 corresponds to PWM5/6.

Note

All inputs to the C281x PWM block must be scalar values.

Duty cycle

Set the ratio of the PWM waveform pulse duration to the PWM Waveform period.

Duty cycle units

Units for the duty cycle. Valid choices are Clock cycles and Percentages. Changing these units changes the Duty cycle value, and the Waveform period value and Waveform period units selection.

Note

Using percentages can cause some additional computation time in generated code. This may or may not be noticeable in your application.

Logic Pane

Control logic source

Configure the control logic for all PWMs enabled on the Outputs tab. Valid settings are Specify via dialog (default setting) or to Input port.

Specify via Dialog enables PWM control logic settings for each PWM output:

  • Forced high causes the pulse value to be high.

    Active high causes the pulse value to go from low to high.

    Active low causes the pulse value to go from high to low.

    Forced low causes the pulse value to be low.

Input port adds an input port to the PWM block for setting the C2000 ACTRx register. Each PWM uses 2 bits to set the following options:

  • 00 Forced Low

  • 01 Active Low

  • 10 Active High

  • 11 Forced High

Bits 11–0 of the 16–bit Compare Action Control Registers for module A control PWM1-6

Bits 11–0 of the 16–bit Compare Action Control Registers for module B control PWM1-6

For example: If a decimal value of 3222 is read at the input port while using PWM module A, the following PWM settings will be honored:

3222 = 0C96h = 110010010110b

So that:

  • PW1: Active High

  • PW2: Active Low

  • PW3: Active Low

  • PW4: Active High

  • PW5: Forced Low

  • PW6: Forced High

For more information, see the section on Compare Action Control Registers (ACTRA and ACTRB) in the Texas Instruments™ document “TMS320x281x DSP Event Manager (EV) Reference Guide”, literature number SPRU065.

Deadband Pane

Use deadband for PWM#/PWM#

Enables a deadband area without signal overlap at the beginning of particular PWM pair signals. The following figure shows the deadband area.

Deadband prescaler

Number of clock cycles, which, when multiplied by the Deadband period, determines the size of the deadband. Selectable values are 1, 2, 4, 8, 16, and 32.

Deadband period source

Source from which the deadband period is obtained. Select Specify via dialog to enter the values in the Deadband period field or select Input port to use a value, in clock cycles, from the input port.

Note

All inputs to the C281x PWM block must be scalar values.

Deadband period

Value that, when multiplied by the Deadband prescaler, determines the size of the deadband. Selectable values are from 1 to 15.

ADC Control Pane

ADC start event

Controls whether this PWM and ADC associated with the same EV module are synchronized. Select None to disable synchronization or select an event to generate the source start-of-conversion (SOC) signal for the associated ADC.

  • None — The ADC and PWM are not synchronized. The EV does not generate an SOC signal and the ADC is triggered by software (that is, the A/D conversion occurs when the ADC block is executed in the software).

  • Underflow interrupt — The EV generates an SOC signal for the ADC associated with the same EV module when the board's general-purpose (GP) timer counter reaches a hexadecimal value of FFFF.

  • Period interrupt — The EV generates an SOC signal for the ADC associated with the same EV module when the value in GP timer matches the value in the period register. The value set in Waveform period above determines the value in the register.

    Note

    If you select Period interrupt and specify a sampling time less than the specified (Waveform period)/(Event timer clock speed), zero-order hold interpolation will occur. (For example, if you enter 64000 as the waveform period, the period for the timer is 64000/75 MHz = 8.5333e-004. If you enter a Sample time in the C281x ADC dialog box that is less than this result, it will cause zero-order hold interpolation.)

  • Compare interrupt — The EV generates an SOC signal for the ADC associated with the same EV module when the value in the GP timer matches the value in the compare register. The value set in Duty cycle above determines the value in the register.