Inter-Processor Communication Using IPC Blocks

This example shows how to use the IPC blocks to communicate between multiple cores of multi-core of Texas Instruments™ C2000™ processors using Simulink® models.

In this example, you will learn how to:

  • Send scalar and vector data from one core using IPC Transmit block

  • Receive data at other core using IPC Receive block in polling and interrupt modes

Required Hardware

  • Texas Instruments™ Delfino F2837xD controlCARDs or F28379D LaunchPad

  • Texas Instruments™ F2838x ControlCard

  • A USB serial cable, if your hardware provides serial over USB capabilities

A USB serial cable is used to establish a serial connection between the host computer and the target hardware. For more information, see Set Up Serial Communication with Target Hardware.

To select a different target hardware, in the Simulink Editor, browse to Configuration Parameters > Hardware Implementation > Hardware board.

Task 1 - Communicate between CPU1 and CPU2 for TI Delfino F2837xD using IPC blocks

This task of an example is configured for TI Delfino F28377D ControlCard with a docking station. F2837xD is a dual-core processor. In this task, You will flash two different models for two cores:

This example uses four different channels to transmit and receive data between cores. The following data is transmitted from CPU1 to CPU2:

  • A scalar uint16 counter value is sent from channel 0

  • Scalar data of type uint32 is sent from channel 1

  • A vector [1x10] of type uint16 is sent from channel 2

  • A vector [1x3] of type single is sent from channel 3

CPU1 model for TI F2837xD (C28x)

Open the c2837xd_ipc_cpu1_tx model, and click Build, Deploy & Start under Hardware tab or press Ctrl+B to build and download the executable file on CPU1.

CPU2 model for TI F2837xD (C28x)

CPU2 receives data using IPC Receive Block in Polling and Interrupt Modes.

1. Open the c2837xd_ipc_cpu2_rx model.

2. In the Configuration Parameters window, click Hardware Implementation and navigate to Target hardware resources > External mode and set the Serial port parameter to the COM port at Device Manager > Ports (COM & LTP) in Windows. For more information, see Parameter Tuning and Signal Logging with Serial Communication.

3. Open Hardware tab and Click Monitor & Tune.

4. Observe the output data using display blocks. The data received in CPU2 must match the data transmitted from CPU1.

Note: The channel number of the IPC Receive block on the reading CPU must match the channel number of the IPC Transmit block on the writing CPU.

Memory Details

For inter-processor communication:

  • For scalar data transfers, message RAMs will be used. The current memory settings in the linker file are:

CPU2TOCPU1RAM: origin = 0x03F800, length = 0x000400

CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

  • For vector data transfers, the two blocks of global shared RAM (2x16K) are used. The current memory settings in the linker file are:

RAMGS_IPCBuffCPU1 : origin = 0x00C000, length = 0x001000

RAMGS_IPCBuffCPU2 : origin = 0x00D000, length = 0x001000

You can access the linker file by browsing to Configuration Parameters > Hardware Implementation > Target hardware resources > Build Options.

For larger data transfers using IPC blocks, the memory must be increased using the linker file. To increase the IPC memory size, allocate more memory for RAMGS_IPCBuffCPU1 and RAMGS_IPCBuffCPU2. The size of the memory must be the same in both cases.

For dual motor control using IPC blocks, see Permanent Magnet Synchronous Motor Field-Oriented Control. In this example, c28379Dpmsmfocdual_cpu1_ert.slx and c28379Dpmsmfocdual_cpu2_ert.slx models communicate using IPC.

Task 2 - Communicate between CPU1, CPU2 on TI F2838x (C28x) and TI F2838x (ARM Cortex -M4) using IPC blocks

This task of an example is configured with Texas Instruments™ F2838x ControlCard. F2838x is a Multi-core processor. You can flash three different models for three cores.

This example uses four different channels to transmit and receive data between cores.

  • A Free-Running counter data is transmitted from CPU1 to CPU2. Data is transmitted at four different sample rates through four channels (0, 1, 2, 3)

  • The data is received at CPU2 using IPC receive blocks. The channel numbers and sample time are configured to match the channel numbers and sample time used in IPC Transmit blocks in CPU1. The received data is then transferred from CPU2 to ARM Cortex - M4.

  • The data is received at ARM Cortex - M4 using IPC receive blocks. The channel numbers and sample time are configured to match the channel numbers and sample time used in IPC Transmit blocks in CPU2. The received data is then transferred from ARM Cortex - M4 to CPU1.

  • Run the CPU1 model in External mode and compare the data sent to CPU2 with the data received from ARM Cortex - M4.

In order to run the example. Download the CPU2 model for TI F2838x (C28x) and ARM Cortex -M4 model ( TI F2838x (ARM Cortex - M4)) and then run CPU1 model for TI F2838x (C28x) in External mode.

CPU2 model for TI F2838x (C28x)

Open the CPU2 model, and click Build, Deploy & Start under Hardware tab or press Ctrl+B to build and download the executable file on CPU2.

ARM Cortex - M4 model for TI F2838x (ARM Cortex - M4)

Open the ARM Cortex-M4 model, and click Build, Deploy & Start under Hardware tab or press Ctrl+B to build and download the executable file on ARM Cortex - M4.

CPU1 model for TI F2838x (C28x)

1. Open CPU1 model.

2. In the Configuration Parameters window, click Hardware Implementation and navigate to Target hardware resources > External mode and set the Serial port parameter to the COM port at Device Manager > Ports (COM &LTP) in Windows. For more information, see Parameter Tuning and Signal Logging with Serial Communication.

3. Open Hardware tab and click Monitor & Tune.

4. Observe the output data using Display blocks. The data received from ARM Cortex - M4 will be delayed value when compared with the data transmitted to CPU2.

Memory Details

For inter-processor communication between CPU1 and CPU2,

  • For scalar data transfers, message RAMs will be used. The current memory settings in the linker file are:

CPU1TOCPU2RAM: origin = 0x03A000, length = 0x000800

CPU2TOCPU1RAM: origin = 0x03B000, length = 0x000800

  • For vector data transfers, the two blocks of the global shared RAM (2x16k) are used. The current memory settings in the linker file are:

RAMGS_IPCBuffCPU1 : origin = 0x00D000, length = 0x001000

RAMGS_IPCBuffCPU2 : origin = 0x00E000, length = 0x001000

For larger data transfers using IPC blocks, the memory must be increased using the linker file. You can access the linker file by browsing to Configuration Parameters > Hardware Implementation > Target hardware resources > Build Options. To increase the IPC memory size, allocate more memory for RAMGS_IPCBuffCPU1 and RAMGS_IPCBuffCPU2. The size of the memory must be the same in both cases.

For inter-processor communication between CPU1/CPU2 and ARM Cortex - M4, as global shared RAM is not available, IPC message RAM is used. The amount of data transfer between CPU1/CPU2 and ARM Cortex - M4 is limited by the size of the message RAMs available.

The current message RAM settings in the linker file are:

CPUTOCMRAM : origin = 0x039000, length = 0x000800

CMTOCPURAM : origin = 0x038000, length = 0x000800

For information about IPC blocks, see: