AXI4 Write

Write data to IP core on the target hardware through AXI4-Lite interface

Description

Use the AXI4 interface to write vector data from the embedded processor to a contiguous group of registers on the Programmable Logic IP Core. The AXI4 Write block only supports the AXI4-Lite protocol, allowing for simple, low-throughput memory-mapped communication. Typical uses for this protocol include writing to control and status registers.

The sample rate of the block input signal controls how often this block writes data to the register.

Ports

Input

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The 1-D vector written to the registers on the IP core starting at Offset address from the base address of the IP core.

Data Types: single | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Parameters

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Enter the path and file name of the IP core device.

Note

If you are using HDL Coder™ to generate the IP core, the IP core is mapped to /dev/mwipcore.

Enter the offset from the base address of the IP core to the register. The block reads data from this register. Use the hex2dec function when you specify the offset address using a hexadecimal number expressed as a character vector.

Note

Using HDL Coder to generate the IP core, you can get the value of the offset address from the Register Address Mapping portion of the Custom IP Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).

Introduced in R2014b