AXI4 Read

Read data from IP core on target hardware through the AXI4-Lite interface

  • Library:
  • Embedded Coder Support Package for Intel SoC Devices

Description

Use the AXI4-Lite interface to read a data vector from a contiguous group of registers on the Programmable Logic IP Core into the embedded processor. The AXI4 Read block only supports the AXI4-Lite protocol, allowing for simple, low-throughput memory-mapped communication. Typical uses for this protocol include reading from control and status registers.

Ports

Output

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The N-by-1 vector read from the registers on the IP core starting at Offset address from the base address of the IP core.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Parameters

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Enter the path and file name of the IP core device.

Note

If you are using HDL Coder™ to generate the IP core, the IP core is mapped to /dev/mwipcore.

Enter the offset from the base address of the IP core to the register. The block reads data from this register. Use the hex2dec function when you specify the offset address using a hexadecimal number expressed as a character vector.

Note

Using HDL Coder to generate the IP core, you can get the value of the offset address from the “Register Address Mapping” portion of the Custom IP Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).

Enter the data type used by the IP core.

Enter the size of the data vector read from the IP core device.

Enter the sample time in seconds. This block polls the register on the IP core for data. When the Sample time is set to -1, the base-rate of the subsystem that contains this block determines the polling frequency.

Introduced in R2014b