Read data from IP core on target hardware through the AXI4-Lite interface
Embedded Coder Support Package for Intel SoC Devices
Use the AXI4-Lite interface to read a data vector from a contiguous group of registers on the Programmable Logic IP Core into the embedded processor. The AXI4 Read block only supports the AXI4-Lite protocol, allowing for simple, low-throughput memory-mapped communication. Typical uses for this protocol include reading from control and status registers.
Port_1— Output signal
The N-by-1 vector read from the registers on the IP core starting at
Offset address from the base address of the IP
Device name— Path and file name of IP core device
Enter the path and file name of the IP core device.
If you are using HDL Coder™ to generate the IP core, the IP core is mapped to
Offset address— Offset from the base address of the IP core to the register
Enter the offset from the base address of the IP core to the register. The
block reads data from this register. Use the
hex2dec function when you
specify the offset address using a hexadecimal number expressed as a
Data type— Data type used by IP core
Enter the data type used by the IP core.
Output vector size— Size of data vector from IP core
Enter the size of the data vector read from the IP core device.
Sample time— Sample time
Enter the sample time in seconds. This block polls the register on the IP
core for data. When the
Sample time is set to
-1, the base-rate of the subsystem that contains this
block determines the polling frequency.