This example shows you how to use Embedded Coder™ Support Package for Intel® SoC Devices for code verification and validation using PIL and External Mode.
In this example you will learn how to configure a Simulink model to run Processor-In-the-Loop (PIL) and External Mode simulations. In a PIL simulation, the generated code runs on a Intel SoC hardware. The results of the PIL simulation are transferred to Simulink to verify the numerical equivalence of the simulation and the code generation results. The PIL verification process is a crucial part of the design cycle to ensure that the behavior of the deployment code matches the design.
Simulink's External mode feature enables you to accelerate the process of parameter tuning by letting you change certain parameter values while the model is running on target hardware, without stopping the model. When you change parameter values from within Simulink, the modified parameter values are communicated to the target hardware immediately. The effects of the parameters tuning activity may be monitored by viewing algorithm signals on scopes or displays in Simulink.
This example introduces the Simulink code generation and verification workflow by showing you how to:
Configure a Simulink model to run PIL simulations on the Intel SoC hardware
Configure a Simulink model to run External Mode simulation on Intel SoC hardware
We recommend completing Getting Started with Embedded Coder Support Package for Intel SoC Devices example.
Intel® SoC FPGA Embedded Design Suite (version 13.1 or later)
To run this example you will need one of the following Intel SoC FPGA hardware:
Altera Cyclone V SoC development board
Arrow SoCKit development board
This example shows how the automatically generated PIL block can be used for verification. With this approach:
You can verify code generated for subsystems
You must provide a test harness model to supply test vector or stimulus inputs
You must swap your original subsystem with an automatically generated PIL block; you should be careful to avoid saving your model in this state as you would lose your original subsystem
1. Open the PIL Block model. This model is configured for Altera Cyclone V SoC development kit. The objective here is to create a PIL block out of the Controller subsystem running on the Intel SoC FPGA hardware.
2. Enable PIL feature by following the steps below:
3. Create a PIL block for the Controller subsystem by following the steps below:
4. Run PIL simulation:
5. Once you start simulating the model, the executable starts running the on the hardware. You can switch between the original and PIL block subsystems by double clicking on the Manual Switch block. Double click on the Numerical Differences block to see the difference between the simulated Controller subsystem and the PIL block running on the hardware.
This example shows how you can verify the automatically generated code for a referenced model by running a PIL simulation. With this approach:
You can verify code generated for referenced models
You must provide a test harness model to provide test vector or stimulus inputs
You can easily switch a Model block between normal and PIL simulation mode
1. Open Model Block PIL model. This model is configured for Altera Cyclone V SoC development board. The model contains two Model blocks that both point at the same referenced model. You will configure one of the Model blocks to run in PIL simulation mode and the other in normal mode.
2. Configure and run CounterA Model block in PIL simulation mode by following the steps below:
3. When model starts running, Scope1 displays the PIL simulation output running on the hardware while Scope2 shows the normal mode simulation output.
This example shows how you can verify the automatically generated code for a top model by running a PIL simulation. With this approach:
You can verify code generated for a top model
You must configure the model to load test vectors or stimulus inputs from the MATLAB workspace
You can easily switch the entire model between normal and PIL simulation mode
1. Open the Top Model PIL model. This model is configured for Altera Cyclone V SoC development board. You will run the model PIL simulation mode.
2. Run the entire model in PIL simulation mode by following the steps below:
3. When the PIL simulation is completed, a logsOut variable is created in the base workspace. The logsOut data contains PIL simulation results. You can access the logged data for signals count_a and count_b using the following commands:
count_a = logsOut.get('count_a');
count_b = logsOut.get('count_b');
In this task, you will run a Simulink model in External simulation mode. When you are prototyping and developing an algorithm, it is useful to monitor and tune the algorithm while it runs on hardware. The External mode feature in Simulink enables this capability.
1. Open the External Mode model. This model is configured for Altera Cyclone V SoC development board. You will run the model in External simulation mode.
2. Configure the model for External Mode simulation, and start the simulation:
In this step, the simulation stop time is set to 'inf' to run the simulation until you explicitly pause or stop the model.
Wait for the model to finish getting built and downloaded onto the target. Once this is done, the External mode simulation will begin. Double click the Manual Switch block while simulation is running to change the input source. Double click on the Gain block to change the signal gain. Finally, double click on the Scope block to view the External mode simulation results. Note that the entire model is running on the hardware.
3. Stop External mode simulation:
Please note: At any point during the course of the External mode simulation, you can open the External Mode Control Panel, using the following instructions:
This example introduced the workflow for code verification using target connectivity features PIL and External Mode.