VHDL Architecture and Library Name and Code for Model Reference Parameters

This page describes parameters that reside in the HDL Code Generation > Global Settings > General tab of the Configuration Parameters dialog box.

VHDL architecture name

Specify the architecture name for your DUT in the generated HDL code.

Settings

Default: 'rtl'

Specify the VHDL architecture name for your DUT in the generated HDL code as a character vector.

Command-Line Information

Property: VHDLArchitectureName

Type: character vector

Default: 'rtl'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'VHDLArchitectureName','_rtl2')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'VHDLArchitectureName','_rtl2')
makehdl('myDUT')
```

VHDL library name

Specify the target library name for the generated VHDL^® code.

Settings

Default: 'work'

Target library name for generated VHDL code.

Command-Line Information

Property: VHDLLibraryName

Type: character vector

Default: 'work'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'VHDLLibraryName','__work1')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'VHDLLibraryName','__work1')
makehdl('myDUT')
```

Generate VHDL or SystemVerilog code for model references into a single library

Specify whether VHDL or SystemVerilog code generated for model references is in a single library, or in separate libraries.

Settings

Default: Off

On: Generate VHDL or SystemVerilog code for model references into a single library.
Off: For each model reference, generate a separate VHDL or SystemVerilog library.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL or SystemVerilog.

Command-Line Information

Property: UseSingleLibrary

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'UseSingleLibrary','on')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'UseSingleLibrary','on')
makehdl('myDUT')
```