Tool and Device Parameters

This page describes the configuration parameters in the Tool and Device Settings section of the HDL Code Generation > Target pane of the Configuration Parameters dialog box. Use the parameters in this section to specify the synthesis tool and settings for your target device.

Target Platform

Specify the target platform which to deploy the generated HDL code. The Workflow and Synthesis Tool parameter values determine the available options for this parameter. When Workflow is set to Generic ASIC/FPGA, Target Platform has no options available.

Settings

Default: ''

Select the target platform from the drop-down menu options.

Command-Line Information

Property: TargetPlatform

Type: character vector

Value: A valid target platform

Default: ''

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to set a target platform to deploy the generated HDL code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','TargetPlatform','Xilinx Zynq ZC702 evaluation kit')

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','TargetPlatform','Xilinx Zynq ZC702 evaluation kit')
makehdl('sfir_fixed/symmetric_fir')
```

Synthesis Tool

Specify the synthesis tool for targeting the generated HDL code. To use HDL Coder™ with one of the supported third-party FPGA synthesis tools, add the tool to the system path using the hdlsetuptoolpath function. When you specify the Synthesis Tool, HDL Coder populates the Family, Device, Package, and Speed with default values for that tool. The Tool Path and Tool Version display the synthesis tool path and tool version respectively of the Synthesis Tool that you specify.

Settings

Default: No synthesis tool specified

The options are:

No synthesis tool specified: Select this option if you do not want to perform logic synthesis. You can generate HDL code from your design.
Xilinx Vivado: Specify Xilinx^® Vivado as the synthesis tool.
Xilinx ISE: Specify Xilinx ISE as the synthesis tool.
Altera Quartus II: Specify Altera^® Quartus II as the synthesis tool.
Microchip Libero SoC: Specify Microchip Libero^® SoC as the synthesis tool.
Intel Quartus Pro: Specify Intel^® Quartus^® Pro as the synthesis tool.

If your synthesis tool is not one of the Synthesis tool options, see Synthesis Tool Path Setup.

Command-Line Information

Property: SynthesisTool

Type: character vector

Value: '' | 'Xilinx Vivado'

'Xilinx
                            ISE'

'Altera Quartus II'

Default: ''

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify Altera Quartus II as the SynthesisTool when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'SynthesisTool','Altera Quartus II')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','SynthesisTool','Altera Quartus II')
makehdl('sfir_fixed/symmetric_fir')
```

Restrictions

When you specify the target language to SystemVerilog, do not select Xilinx ISE as Synthesis tool. Xilinx ISE does not support SystemVerilog HDL language.

Family

Specify the target device chip family for your model as a character vector. When you specify the Synthesis Tool, HDL Coder populates the Family, Device, Package, and Speed with default values for that tool. To find the chip family for your target device, at the MATLAB^® command line, enter hdlcoder.supportedDevices. Then, open the linked report and find your target device details.

Settings

Default: ''

Specify the target device chip family for your Simulink^® model as a character vector.

Command-Line Information

Property: SynthesisToolChipFamily

Type: character vector

Value: A valid chip family for the target device

Default: ''

For example, if your SynthesisTool is Xilinx Vivado, you can specify Virtex7 as the SynthesisToolChipFamily when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'SynthesisToolChipFamily', 'Virtex7')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','SynthesisToolChipFamily', 'Virtex7')
makehdl('sfir_fixed/symmetric_fir')
```

Device

Specify the target device name for your model as a character vector. When you specify the Synthesis Tool, HDL Coder populates the Family, Device, Package, and Speed with default values for that tool. To find the device name for your target device, at the MATLAB command line, enter hdlcoder.supportedDevices. Then, open the linked report and find your target device details.

Settings

Default: ''

Specify the target device name for your Simulink model as a character vector.

Command-Line Information

Property: SynthesisToolDevicename

Type: character vector

Value: A valid device name for the synthesis tool

Default: ''

You can get the SynthesisToolDeviceName when you specify the SynthesisTool for your model. Consider that the SynthesisTool is set to Xilinx Vivado and the SynthesisToolChipFamily is set to Virtex7.

To get the default device name. pass the property as an argument to the hdlget_param function.
```
hdlget_param('sfir_fixed', ... 
        'SynthesisToolDeviceName')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','SynthesisToolDeviceName', 'xc7v2000t')
makehdl('sfir_fixed/symmetric_fir')
```

Package

Specify the target device package name for your model as a character vector. When you specify the Synthesis Tool, HDL Coder populates the Family, Device, Package, and Speed with default values for that tool. To find the device name for your target device, at the MATLAB command line, enter hdlcoder.supportedDevices. Then, open the linked report and find your target device details.

Settings

Default: ''

Specify the target device package name for your Simulink model as a character vector.

Command-Line Information

Property: SynthesisToolPackageName

Type: character vector

Value: A valid package name for the synthesis tool

Default: ''

You can get the SynthesisToolPackageName when you specify the SynthesisTool for your model. Consider that the SynthesisTool is set to Xilinx Vivado and the SynthesisToolChipFamily is set to Virtex7.

To get the default device name. pass the property as an argument to the hdlget_param function.
```
hdlget_param('sfir_fixed', ... 
        'SynthesisToolPackageName')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','SynthesisToolPackageName', 'fhg1761')
makehdl('sfir_fixed/symmetric_fir')
```

Speed

Specify the target device speed value for your model as a character vector. When you specify the Synthesis Tool, HDL Coder populates the Family, Device, Package, and Speed with default values for that tool. To find the chip family for your target device, at the MATLAB command line, enter hdlcoder.supportedDevices. Then, open the linked report and find your target device details.

Settings

Default: ''

Specify the target device speed value for your Simulink model as a character vector.

Command-Line Information

Property: SynthesisToolSpeedValue

Type: character vector

Value: A valid speed value for the target device

Default: ''

You can get the SynthesisToolSpeedValue when you specify the SynthesisTool for your model. Consider that the SynthesisTool is set to Xilinx Vivado and the SynthesisToolChipFamily is set to Virtex7.

To get the default device name. pass the property as an argument to the hdlget_param function.
```
hdlget_param('sfir_fixed', ... 
        'SynthesisToolSpeedValue')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','SynthesisToolSpeedValue', '-1')
makehdl('sfir_fixed/symmetric_fir')
```