Test Bench Generation Output Parameters

To specify the type of test bench to generate for verifying the HDL code in a simulation tool, use the Test Bench Generation Output parameters setting. You can specify the configuration parameters for the test bench generation in HDL Code Generation > Test Bench > Test Bench Generation Output. This setting is enabled when you select the subsystem in your model. Select the subsystem in your model from the Generate HDL for menu on the parent HDL Code Generation pane, and then initiate the test bench generation for the subsystem. This setting is unavailable if you select the entire model.

HDL test bench

Enable or disable HDL test bench generation.

Settings

Default: selected

On

Enable generation of HDL test bench code. The code generator creates a HDL test bench by running a Simulink^® simulation to capture input vectors and expected output data for your DUT.

This test bench is the default test bench that HDL Coder™ generates for your model. If you have not already generated code for your model, running HDL test bench generation also generates code for your DUT.

Specify your HDL simulator in the Simulation tool menu. HDL Coder generates build-and-run scripts for the simulator that you specify.

Off

Suppress generation of HDL test bench code. You can use this option when you use an alternate test bench.

Dependencies

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

This check box enables the options in the Configuration section of the Test Bench pane. Select a Simulation tool to generate scripts to build and run the test bench.

Command-Line Information

Property: GenerateHDLTestBench

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, to generate a HDL test bench for the sfir_fixed/symmetric_fir Subsystem, pass the DUT as an argument to the makehdltb function.

makehdltb('sfir_fixed/symmetric_fir')

Cosimulation model

Enable or disable generation of a model including a HDL Cosimulation block. This option requires an HDL Verifier™ license. After you select this check box, specify your Simulation tool. You can select Mentor Graphics^® ModelSim^®, Cadence Incisive^®, or Xilinx^® Vivado^® Simulator for cosimulation. Custom script settings are not supported with this test bench.

The code generator configures the generated HDL Cosimulation blocks to conform to the port and data type interface of the DUT selected for code generation. By connecting an HDL Cosimulation block to your model in place of the DUT, you can cosimulate your design with the desired simulator.

The coder appends the character vector that the CosimLibPostfix property specifies to the names of the generated HDL Cosimulation blocks.

Settings

Default: not selected

Dependencies

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

Command-Line Information

Property: GenerateCoSimBlock

Type: character vector

Value: 'on' | 'off'

Default: 'off'

Property: GenerateCoSimModel

Type: character vector

Value: 'ModelSim' | 'Incisive' | 'Vivado Simulator' | 'None'

Default: 'ModelSim'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can enable the GenerateCoSimModel property when you generate a testbench for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdltb function.

makehdltb('sfir_fixed/symmetric_fir', ... 
            'GenerateCoSimModel','ModelSim')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.
```
hdlset_param('sfir_fixed','GenerateCoSimModel','ModelSim')
makehdltb('sfir_fixed/symmetric_fir')
```

SystemVerilog DPI test bench

Enable or disable generation of SystemVerilog DPI test bench. Select your HDL simulator at Simulation tool. For SystemVerilog DPI test bench you can select Mentor Graphics ModelSim, Cadence Incisive, Synopsys^® , or Xilinx Vivado. The command line option also includes a VCS^® simulator. Custom script settings are not supported with this test bench.

When you set this property, the code generator generates a direct programming interface (DPI) component for your entire Simulink model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The code generator generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The coder also builds shared libraries and generates a simulation script for the simulator you select.

Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file.

To use this capability, you must have HDL Verifier and Simulink Coder. To run the SystemVerilog test bench with generated VHDL code, you must have a mixed-language simulation license for your HDL simulator.

Settings

Default: not selected

Dependencies

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

Limitations

Your DUT subsystem must meet the following conditions:

Input and output data types of the DUT cannot be larger than 64 bits.
Input and output ports of the DUT cannot use enumerated data types.
Input and output ports cannot be single-precision or double-precision data types.
The DUT cannot have multiple clocks. You must set the Clock inputs code generation option to Single.
Use trigger signal as clock must not be selected.
If the DUT uses vector ports, you must use Scalarize vector ports to flatten the interface.

Command-Line Information

Property: GenerateSVDPITestBench

Type: character vector

Value: 'ModelSim' | 'Incisive'|'Custom'|'VCS'|

'Vivado
                            Simulator'

Default: 'ModelSim'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can enable the GenerateCoSimModel property when you generate a testbench for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdltb function.

makehdltb('sfir_fixed/symmetric_fir', ... 
            'GenerateSVDPITestBench','ModelSim')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.
```
hdlset_param('sfir_fixed','GenerateSVDPITestBench','ModelSim')
makehdltb('sfir_fixed/symmetric_fir')
```

Simulation tool

Simulator where you run the generated test benches. The tool generates a script to build and run your HDL code and test bench.

Settings

Mentor Graphics ModelSim: This option is the default. HDL Coder generates the selected types of test benches for use with Mentor Graphics ModelSim.
Cadence Incisive: The coder generates the selected types of test benches for use with Cadence Incisive.
Xilinx Vivado Simulator: The coder generates the selected types of test benches for use with Xilinx Vivado simulator.
Custom: Selecting this option enables the custom script options on the EDA Tool Scripts pane.
VCS: This simulator is supported only for SystemVerilog DPI test bench.

Dependencies

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

Command-Line Information

For HDL test bench, use the SimulationTool property. For cosimulation, use the GenerateCosimModel property. For SystemVerilog DPI test bench, use the GenerateSVDPITestbench property.

Property: SimulationTool

Type: character vector

Value: 'Mentor Graphics ModelSim' |

'Cadence
                            Incisive'

| 'Xilinx Vivado Simulator' | 'Custom'

Default: 'Mentor Graphics ModelSim'

Property: GenerateCosimModel

Type: character vector

Value: 'ModelSim' | 'Incisive' | 'Vivado Simulator' | 'None'

Default: 'ModelSim'

Property: GenerateSVDPITestbench

Type: character vector

Value: 'ModelSim' | 'Incisive'|'Custom'|'VCS'|'Vivado'

Default: 'ModelSim'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

HDL code coverage

Enable or disable HDL code coverage flags in the generated simulator scripts

With this option enabled, when you run the HDL simulation, code coverage is collected for your generated test bench. Specify your HDL simulator in the SimulationTool property. The coder generates build-and-run scripts for the simulator you specify.

Settings

Default: not selected

Dependencies

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

This option is ignored when GenerateCoSimBlock is selected and SimulationTool is set to 'Xilinx Vivado Simulator'.

Command-Line Information

Property: HDLCodeCoverage

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can enable the HDLCodeCoverage property when you generate a testbench for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdltb function.

makehdltb('sfir_fixed/symmetric_fir', ... 
            'HDLCodeCoverage','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.
```
hdlset_param('sfir_fixed','HDLCodeCoverage','on')
makehdltb('sfir_fixed/symmetric_fir')
```