Main Content

RTL Style Parameters

You access the register transfer logic (RTL) style parameters in the HDL Code Generation > Global Settings > Coding Style tab in the Configuration Parameters dialog box.

Use “rising_edge/falling_edge” style for registers

Specify whether generated code uses the VHDL® rising_edge function or the falling_edge function to detect clock transitions.

Settings

Default: Off

On

Generated code uses either the rising_edge function or the falling_edge function.

For example, this following code generated from a Unit Delay block uses the rising_edge function to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF rising_edge(clk) THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Off

Generated code uses the 'event syntax.

For example, this code generated from a Unit Delay block uses clk'event AND clk = '1' to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Dependency

This option is enabled when the target language is VHDL.

Command-Line Information

Property: UseRisingEdge
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Minimize intermediate signals

Specify whether to optimize HDL code for debuggability or code coverage.

Settings

Default: Off

On

Optimize the code coverage by minimizing intermediate signals. For example, with this setting as off, suppose that the generated code is:

const3 <= to_signed(24, 7);
subtractor_sub_cast <= resize(const3, 8);
subtractor_sub_cast_1 <= resize(delayout, 8);
subtractor_sub_temp <= subtractor_sub_cast - subtractor_sub_cast_1;

With this setting as on, HDL Coder™ optimizes the output to:

subtractor_sub_temp <= 24 - (resize(delayout, 8));

The code generator removes the intermediate signals const3, subtractor_sub_cast, and subtractor_sub_cast_1.

Off

Optimize the code for debuggability by preserving intermediate signals.

Command-Line Information

Property: MinimizeIntermediateSignals
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Unroll For-Generate Loops in VHDL code

Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code.

Settings

Default: Off

On

Unroll and omit FOR and GENERATE loops from the generated VHDL code. (In Verilog® code, loops are always unrolled.)

Off

Include FOR and GENERATE loops in the generated VHDL code.

Command-Line Information

Property: LoopUnrolling
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For some Simulink® blocks, by default, the HDL code is generated by using a FOR-GENERATE loop construct when you set the target language to VHDL. These Simulink blocks are:

The code generated by using a FOR-GENERATE loop has better code readability, reduced lines of code, and reduced code generation time. For example, consider the VHDL code generated for reshaping a 2-D matrix into a 1-D matrix. The example shows the code generated for the Reshape block with and without a FOR-GENERATE loops.

  • Reshape block without a FOR-GENERATE loop (Unroll for Generate Loops for VHDL code is enabled):

Reshape_output : PROCESS (In1_signed)
BEGIN
Reshape_out1(0) <= In1_signed(0, 0);
Reshape_out1(1) <= In1_signed(1, 0);
Reshape_out1(2) <= In1_signed(2, 0);
Reshape_out1(3) <= In1_signed(3, 0);
Reshape_out1(4) <= In1_signed(4, 0);
Reshape_out1(5) <= In1_signed(5, 0);
Reshape_out1(6) <= In1_signed(6, 0);
Reshape_out1(7) <= In1_signed(7, 0);
Reshape_out1(8) <= In1_signed(8, 0);
Reshape_out1(9) <= In1_signed(9, 0);
Reshape_out1(10) <= In1_signed(0, 1);
...

  • Reshape block with a FOR-GENERATE loop (Unroll for Generate Loops for VHDL code is disabled):

Reshape_out1GEN_LABEL1: FOR d1 IN 0 TO 1 GENERATE
  Reshape_out1GEN_LABEL: FOR d0 IN 0 TO 9 GENERATE
     Reshape_out1(d0 + (d1*10)) <= In1_signed(d0, d1);
  END GENERATE;
END GENERATE;

Tips

  • If you are using an electronic design automation (EDA) tool that does not support GENERATE loops, select loop unrolling option to omit loops from your generated VHDL code.

  • Setting the loop unrolling option does not affect results obtained from simulation or synthesis of generated VHDL code.

Dependency

This option is enabled when the target language is VHDL.

Generate parameterized HDL code from masked subsystem

Generate reusable HDL code for subsystems that have the same tunable mask parameters, but with different values.

Settings

Default: Off

On

Generate one reusable HDL file for multiple masked subsystems that have different values for the mask parameters. HDL Coder supports scalar, vector, and matrix values as mask parameters. HDL Coder detects subsystems that have tunable mask parameters, which are sharable.

Inside the subsystem, you can use the mask parameter only in the blocks and parameters listed in the table.

Block ParameterLimitation
Constant Constant value on the Main tab in the dialog boxNone
GainGain on the Main tab in the dialog boxParameter data type must be the same for all Gain blocks.
Off

Generate a separate HDL file for each masked subsystem.

Command-Line Information

Property: MaskParameterAsGeneric
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Restrictions for Mask Parameter Values

  • Each value must be a scalar, vector, or matrix.

  • Values must not be complex.

  • Values must not be enumerated data.

See Also

Generate Reusable Code for Subsystems

Enumerated Type Encoding Scheme

Specify the encoding scheme to represent enumeration types in the generated HDL code.

Settings

Default: default

Use a default, onehot, twohot, or binary encoding scheme to represent enumerated types in the generated HDL code.

default

The code generator uses decimal encoding in Verilog and VHDL-native enumerated types in VHDL. This example shows the Verilog code snippet of this encoding scheme for a Stateflow® Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'd0, 
is_Chart_IN_s_rx = 2'd1, 
is_Chart_IN_s_wait_0 = 2'd2, 
is_Chart_IN_s_wait_tb = 2'd3;

onehot

The code generator uses a one-hot encoding scheme where a single bit is high to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0001, 
is_Chart_IN_s_rx = 4'b0010, 
is_Chart_IN_s_wait_0 = 4'b0100, 
is_Chart_IN_s_wait_tb = 4'b1000;
This encoding scheme does not support more than 64 enumeration values or numbers of states.

twohot

The code generator uses a two-hot encoding scheme where two bits are high to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0011, 
is_Chart_IN_s_rx = 4'b0101, 
is_Chart_IN_s_wait_0 = 4'b0110, 
is_Chart_IN_s_wait_tb = 4'b1001;

binary

The code generator uses a binary encoding scheme to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'b00, 
is_Chart_IN_s_rx = 2'b01, 
is_Chart_IN_s_wait_0 = 2'b10, 
is_Chart_IN_s_wait_tb = 2'b11;

In VHDL, the generated code uses CONSTANT types to encode nondefault enumeration values in the generated code. For example, this code snippet shows the generated VHDL code when you use the two-hot state encoding for a Stateflow Chart that has four states.

 PACKAGE s_pkg IS
  -- Constants
  -- Two-hot encoded enumeration values for type state_type_is_Chart
  CONSTANT IN_s_idle         : std_logic_vector(3 DOWNTO 0) := 
    "0011";
  CONSTANT IN_s_rx           : std_logic_vector(3 DOWNTO 0) := 
    "0101";
  CONSTANT IN_s_wait_0       : std_logic_vector(3 DOWNTO 0) := 
    "0110";
  CONSTANT IN_s_wait_tb      : std_logic_vector(3 DOWNTO 0) := 
    "1001";

END s_pkg;

Command-Line Information

Property: EnumEncodingScheme
Type: character vector
Value: 'default' | 'onehot' | 'twohot''binary'
Default: 'default'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.