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Pipelining Parameters

This documentation page describes configuration parameters that reside in the HDL Code Generation > Optimization > Pipelining tab of the Configuration Parameters dialog box. Using the parameters in this section, you can improve the timing of your design on the target device. .

Hierarchical distributed pipelining

Hierarchical distributed pipelining extends the scope of distributed pipelining by distributing delays across subsystem hierarchies. This optimization moves the delays within a Subsystem while preserving the hierarchy.

Settings

Default: Off

On

Enable retiming across a subsystem hierarchy. HDL Coder™ applies retiming hierarchically from the top-level Subsystem. To move delays inside a Subsystem, in the HDL Block Properties for that Subsystem, set DistributedPipelining to on. Hierarchical distributed pipelining stops distributing delays when it reaches a Subsystem that has DistributedPipelining set to off.

Off

Distributes pipelines within a Subsystem, if you have DistributedPipelining set to on for that Subsystem.

Dependency

If you select the Preserve design delays check box, distributed pipelining does not move the design delays.

Command-Line Information

Property: HierarchicalDistPipelining
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can enable the HierarchicalDistPipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'HierarchicalDistPipelining','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','HierarchicalDistPipelining','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Distributed pipelining priority

Specify the priority for your distributed pipelining algorithm.

Settings

Default: Numerical Integrity

Numerical Integrity

Prioritize numerical integrity when distributing pipeline registers.

This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.

Performance

Prioritize performance over numerical integrity.

Use this option if your design requires a higher clock frequency and the Simulink behavior does not need to strictly match the generated code behavior. This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown.

Command-Line Information

Property: DistributedPipeliningPriority
Type: character vector
Value: 'NumericalIntegrity' | 'Performance'
Default: 'NumericalIntegrity'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the DistributedPipeliningPriority setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'DistributedPipeliningPriority','Performance')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','DistributedPipeliningPriority','Performance')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Clock-rate pipelining

If your design contains multicycle paths, use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.

Settings

Default: On

On

Insert pipeline registers at the clock rate for multi-cycle paths.

Off

Insert pipeline registers at the data rate for multi-cycle paths.

Dependency

If you specify an Oversampling factor greater than one, make sure that you select the Clock-rate pipelining check box. Clock-rate pipelining identifies regions in your model that run at the same slow data rate and are delimited by Delay blocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region.

Command-Line Information

Property: ClockRatePipelining
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the ClockRatePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'ClockRatePipelining','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','ClockRatePipelining','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Allow clock-rate pipelining of DUT output ports

For DUT output ports, insert pipeline registers at the clock rate instead of the data rate.

Settings

Default: Off

On

At DUT output ports, insert pipeline registers at clock rate.

Off

At DUT output ports, insert pipeline registers at data rate.

Dependency

When you specify this parameter, make sure that you select the Clock-rate pipelining check box.

Command-Line Information

Property: ClockRatePipelineOutputPorts
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the ClockRatePipelineOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'ClockRatePipelineOutputPorts','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','ClockRatePipelineOutputPorts','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Adaptive pipelining

Use this parameter to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

Settings

Default: On

On

Insert adaptive pipeline registers in your design. For HDL Coder to insert adaptive pipelines, you must specify the synthesis tool.

Off

Do not insert adaptive pipeline registers.

Dependency

When you specify this parameter, in the HDL Code Generation > Targetpane, specify the Synthesis Tool. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.

Command-Line Information

Property: AdaptivePipelining
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the AdaptivePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
                        'AdaptivePipelining','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','AdaptivePipelining','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Preserve design delays

Settings

Default: Off

On

Prevent distributed pipelining from moving design delays.

Off

Do not prevent distributed pipelining from moving design delays.

Command-Line Information

Property: PreserveDesignDelays
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the PreserveDesignDelays setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'PreserveDesignDelays','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','PreserveDesignDelays','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also